Re: [PATCH iwl-next v2] igc: Add MQPRIO offload support

[Kurt Kanzenbach <kurt@linutronix.de>]

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On Wed Mar 27 2024, shenjian (K) wrote:
> 在 2024/3/26 21:34, Kurt Kanzenbach 写道:
>> Add support for offloading MQPRIO. The hardware has four priorities as well
>> as four queues. Each queue must be a assigned with a unique priority.
>>
>> However, the priorities are only considered in TSN Tx mode. There are two
>> TSN Tx modes. In case of MQPRIO the Qbv capability is not required.
>> Therefore, use the legacy TSN Tx mode, which performs strict priority
>> arbitration.
>>
>> Example for mqprio with hardware offload:
>>
>> |tc qdisc replace dev ${INTERFACE} handle 100 parent root mqprio num_tc 4 \
>> |   map 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 \
>> |   queues 1@0 1@1 1@2 1@3 \
>> |   hw 1
>>
>> The mqprio Qdisc also allows to configure the `preemptible_tcs'. However,
>> frame preemption is not supported yet.
>>
>> Tested on Intel i225 and implemented by following data sheet section 7.5.2,
>> Transmit Scheduling.
>>
>> Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de>
>> ---
>> Changes in v2:
>> - Improve changelog (Paul Menzel)
>> - Link to v1: https://lore.kernel.org/r/20240212-igc_mqprio-v1-1-7aed95b736db@linutronix.de
>> ---
>>   drivers/net/ethernet/intel/igc/igc.h         | 10 +++-
>>   drivers/net/ethernet/intel/igc/igc_defines.h |  9 ++++
>>   drivers/net/ethernet/intel/igc/igc_main.c    | 69 +++++++++++++++++++++++++++
>>   drivers/net/ethernet/intel/igc/igc_regs.h    |  2 +
>>   drivers/net/ethernet/intel/igc/igc_tsn.c     | 71 +++++++++++++++++++++++++++-
>>   5 files changed, 157 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h
>> index 90316dc58630..49ba753ce957 100644
>> --- a/drivers/net/ethernet/intel/igc/igc.h
>> +++ b/drivers/net/ethernet/intel/igc/igc.h
>> @@ -227,6 +227,10 @@ struct igc_adapter {
>>   	 */
>>   	spinlock_t qbv_tx_lock;
>>   
>> +	bool strict_priority_enable;
>> +	u8 num_tc;
>> +	u16 queue_per_tc[IGC_MAX_TX_QUEUES];
>> +
>>   	/* OS defined structs */
>>   	struct pci_dev *pdev;
>>   	/* lock for statistics */
>> @@ -346,9 +350,11 @@ extern char igc_driver_name[];
>>   #define IGC_FLAG_RX_LEGACY		BIT(16)
>>   #define IGC_FLAG_TSN_QBV_ENABLED	BIT(17)
>>   #define IGC_FLAG_TSN_QAV_ENABLED	BIT(18)
>> +#define IGC_FLAG_TSN_LEGACY_ENABLED	BIT(19)
>>   
>> -#define IGC_FLAG_TSN_ANY_ENABLED \
>> -	(IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED)
>> +#define IGC_FLAG_TSN_ANY_ENABLED				\
>> +	(IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED |	\
>> +	 IGC_FLAG_TSN_LEGACY_ENABLED)
>>   
>>   #define IGC_FLAG_RSS_FIELD_IPV4_UDP	BIT(6)
>>   #define IGC_FLAG_RSS_FIELD_IPV6_UDP	BIT(7)
>> diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h
>> index 5f92b3c7c3d4..73502a0b4df7 100644
>> --- a/drivers/net/ethernet/intel/igc/igc_defines.h
>> +++ b/drivers/net/ethernet/intel/igc/igc_defines.h
>> @@ -547,6 +547,15 @@
>>   
>>   #define IGC_MAX_SR_QUEUES		2
>>   
>> +#define IGC_TXARB_TXQ_PRIO_0_SHIFT	0
>> +#define IGC_TXARB_TXQ_PRIO_1_SHIFT	2
>> +#define IGC_TXARB_TXQ_PRIO_2_SHIFT	4
>> +#define IGC_TXARB_TXQ_PRIO_3_SHIFT	6
>> +#define IGC_TXARB_TXQ_PRIO_0_MASK	GENMASK(1, 0)
>> +#define IGC_TXARB_TXQ_PRIO_1_MASK	GENMASK(3, 2)
>> +#define IGC_TXARB_TXQ_PRIO_2_MASK	GENMASK(5, 4)
>> +#define IGC_TXARB_TXQ_PRIO_3_MASK	GENMASK(7, 6)
>> +
>>   /* Receive Checksum Control */
>>   #define IGC_RXCSUM_CRCOFL	0x00000800   /* CRC32 offload enable */
>>   #define IGC_RXCSUM_PCSD		0x00002000   /* packet checksum disabled */
>> diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c
>> index 2e1cfbd82f4f..b17764973d74 100644
>> --- a/drivers/net/ethernet/intel/igc/igc_main.c
>> +++ b/drivers/net/ethernet/intel/igc/igc_main.c
>> @@ -6415,6 +6415,13 @@ static int igc_tc_query_caps(struct igc_adapter *adapter,
>>   	struct igc_hw *hw = &adapter->hw;
>>   
>>   	switch (base->type) {
>> +	case TC_SETUP_QDISC_MQPRIO: {
>> +		struct tc_mqprio_caps *caps = base->caps;
>> +
>> +		caps->validate_queue_counts = true;
>> +
>> +		return 0;
>> +	}
>>   	case TC_SETUP_QDISC_TAPRIO: {
>>   		struct tc_taprio_caps *caps = base->caps;
>>   
>> @@ -6432,6 +6439,65 @@ static int igc_tc_query_caps(struct igc_adapter *adapter,
>>   	}
>>   }
>>   
>> +static void igc_save_mqprio_params(struct igc_adapter *adapter, u8 num_tc,
>> +				   u16 *offset)
>> +{
>> +	int i;
>> +
>> +	adapter->strict_priority_enable = true;
>> +	adapter->num_tc = num_tc;
>> +
>> +	for (i = 0; i < num_tc; i++)
>> +		adapter->queue_per_tc[i] = offset[i];
>> +}
>> +
>> +static int igc_tsn_enable_mqprio(struct igc_adapter *adapter,
>> +				 struct tc_mqprio_qopt_offload *mqprio)
>> +{
>> +	struct igc_hw *hw = &adapter->hw;
>> +	int i;
>> +
>> +	if (hw->mac.type != igc_i225)
>> +		return -EOPNOTSUPP;
>> +
>> +	if (!mqprio->qopt.num_tc) {
>> +		adapter->strict_priority_enable = false;
>> +		goto apply;
>> +	}
>> +
>> +	/* There are as many TCs as Tx queues. */
>> +	if (mqprio->qopt.num_tc != adapter->num_tx_queues) {
>> +		NL_SET_ERR_MSG_FMT_MOD(mqprio->extack,
>> +				       "Only %d traffic classes supported",
>> +				       adapter->num_tx_queues);
>> +		return -EOPNOTSUPP;
>> +	}
>> +
>> +	/* Only one queue per TC is supported. */
>> +	for (i = 0; i < mqprio->qopt.num_tc; i++) {
>> +		if (mqprio->qopt.count[i] != 1) {
>> +			NL_SET_ERR_MSG_MOD(mqprio->extack,
>> +					   "Only one queue per TC supported");
>> +			return -EOPNOTSUPP;
>> +		}
>> +	}
> When mqprio enabled for igc, only one queue per TC supported. Is 
> set_channels by ethtool
> allowed in this case ?  If not, it's better to add limitation in 
> icg_ethtool_set_channels.

Note sure about that. I'll have a look.

Thanks,
Kurt

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