[PATCH v3 0/9] ptp .adjphase cleanups

[PATCH v3 0/9] ptp .adjphase cleanups

[Rahul Rameshbabu]

The goal of this patch series is to improve documentation of .adjphase, add
a new callback .getmaxphase to enable advertising the max phase offset a
device PHC can support, and support invoking .adjphase from the testptp
kselftest.

Changes:
  v3->v2:
    * Add information about returning -ERANGE instead of clamping
      out-of-range offsets for driver implementations of .adjphase that
      previously clamped out-of-range offsets.

      Link: https://lore.kernel.org/netdev/13b7315446390d3a78d8f508937354f12778b68e.camel@redhat.com/
  v2->v1:
    * Removes arbitrary rule that the PHC servo must restore the frequency
      to the value used in the last .adjfine call if any other PHC
      operation is used after a .adjphase operation.
    * Removes a macro introduced in v1 for adding PTP sysfs device
      attribute nodes using a callback for populating the data.

Link: https://lore.kernel.org/netdev/20230523205440.326934-1-rrameshbabu@nvidia.com/ 
Link: https://lore.kernel.org/netdev/20230510205306.136766-1-rrameshbabu@nvidia.com/
Link: https://lore.kernel.org/netdev/20230120160609.19160723@kernel.org/

Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Richard Cochran <richardcochran@gmail.com>

Rahul Rameshbabu (9):
  ptp: Clarify ptp_clock_info .adjphase expects an internal servo to be
    used
  docs: ptp.rst: Add information about NVIDIA Mellanox devices
  testptp: Remove magic numbers related to nanosecond to second
    conversion
  testptp: Add support for testing ptp_clock_info .adjphase callback
  ptp: Add .getmaxphase callback to ptp_clock_info
  net/mlx5: Add .getmaxphase ptp_clock_info callback
  ptp: ptp_clockmatrix: Add .getmaxphase ptp_clock_info callback
  ptp: idt82p33: Add .getmaxphase ptp_clock_info callback
  ptp: ocp: Add .getmaxphase ptp_clock_info callback

 Documentation/driver-api/ptp.rst              | 29 +++++++++++++++
 .../ethernet/mellanox/mlx5/core/lib/clock.c   | 31 ++++++++--------
 drivers/ptp/ptp_chardev.c                     |  5 ++-
 drivers/ptp/ptp_clock.c                       |  4 +++
 drivers/ptp/ptp_clockmatrix.c                 | 36 +++++++++----------
 drivers/ptp/ptp_clockmatrix.h                 |  2 +-
 drivers/ptp/ptp_idt82p33.c                    | 18 +++++-----
 drivers/ptp/ptp_idt82p33.h                    |  4 +--
 drivers/ptp/ptp_ocp.c                         |  7 ++++
 drivers/ptp/ptp_sysfs.c                       | 12 +++++++
 include/linux/ptp_clock_kernel.h              | 11 ++++--
 include/uapi/linux/ptp_clock.h                |  3 +-
 tools/testing/selftests/ptp/testptp.c         | 29 ++++++++++++---
 13 files changed, 135 insertions(+), 56 deletions(-)

-- 
2.40.1

[PATCH v3 1/9] ptp: Clarify ptp_clock_info .adjphase expects an internal servo to be used

[Rahul Rameshbabu]

.adjphase expects a PHC to use an internal servo algorithm to correct the
provided phase offset target in the callback. Implementation of the
internal servo algorithm are defined by the individual devices.

Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Acked-by: Richard Cochran <richardcochran@gmail.com>
---

Notes:
    Changes:
    
      v2->v1:
        * Removes arbitrary rule that the PHC servo must restore the frequency
          to the value used in the last .adjfine call if any other PHC operation
          is used after a .adjphase operation.

 Documentation/driver-api/ptp.rst | 16 ++++++++++++++++
 include/linux/ptp_clock_kernel.h |  6 ++++--
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/Documentation/driver-api/ptp.rst b/Documentation/driver-api/ptp.rst
index 664838ae7776..4552a1f20488 100644
--- a/Documentation/driver-api/ptp.rst
+++ b/Documentation/driver-api/ptp.rst
@@ -73,6 +73,22 @@ Writing clock drivers
    class driver, since the lock may also be needed by the clock
    driver's interrupt service routine.
 
+PTP hardware clock requirements for '.adjphase'
+-----------------------------------------------
+
+   The 'struct ptp_clock_info' interface has a '.adjphase' function.
+   This function has a set of requirements from the PHC in order to be
+   implemented.
+
+     * The PHC implements a servo algorithm internally that is used to
+       correct the offset passed in the '.adjphase' call.
+     * When other PTP adjustment functions are called, the PHC servo
+       algorithm is disabled.
+
+   **NOTE:** '.adjphase' is not a simple time adjustment functionality
+   that 'jumps' the PHC clock time based on the provided offset. It
+   should correct the offset provided using an internal algorithm.
+
 Supported hardware
 ==================
 
diff --git a/include/linux/ptp_clock_kernel.h b/include/linux/ptp_clock_kernel.h
index fdffa6a98d79..f8e8443a8b35 100644
--- a/include/linux/ptp_clock_kernel.h
+++ b/include/linux/ptp_clock_kernel.h
@@ -77,8 +77,10 @@ struct ptp_system_timestamp {
  *            nominal frequency in parts per million, but with a
  *            16 bit binary fractional field.
  *
- * @adjphase:  Adjusts the phase offset of the hardware clock.
- *             parameter delta: Desired change in nanoseconds.
+ * @adjphase:  Indicates that the PHC should use an internal servo
+ *             algorithm to correct the provided phase offset.
+ *             parameter delta: PHC servo phase adjustment target
+ *                              in nanoseconds.
  *
  * @adjtime:  Shifts the time of the hardware clock.
  *            parameter delta: Desired change in nanoseconds.
-- 
2.40.1

[PATCH v3 2/9] docs: ptp.rst: Add information about NVIDIA Mellanox devices

[Rahul Rameshbabu]

The mlx5_core driver has implemented ptp clock driver functionality but
lacked documentation about the PTP devices. This patch adds information
about the Mellanox device family.

Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Acked-by: Richard Cochran <richardcochran@gmail.com>
---
 Documentation/driver-api/ptp.rst | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/driver-api/ptp.rst b/Documentation/driver-api/ptp.rst
index 4552a1f20488..5e033c3b11b3 100644
--- a/Documentation/driver-api/ptp.rst
+++ b/Documentation/driver-api/ptp.rst
@@ -122,3 +122,16 @@ Supported hardware
           - LPF settings (bandwidth, phase limiting, automatic holdover, physical layer assist (per ITU-T G.8273.2))
           - Programmable output PTP clocks, any frequency up to 1GHz (to other PHY/MAC time stampers, refclk to ASSPs/SoCs/FPGAs)
           - Lock to GNSS input, automatic switching between GNSS and user-space PHC control (optional)
+
+   * NVIDIA Mellanox
+
+     - GPIO
+          - Certain variants of ConnectX-6 Dx and later products support one
+            GPIO which can time stamp external triggers and one GPIO to produce
+            periodic signals.
+          - Certain variants of ConnectX-5 and older products support one GPIO,
+            configured to either time stamp external triggers or produce
+            periodic signals.
+     - PHC instances
+          - All ConnectX devices have a free-running counter
+          - ConnectX-6 Dx and later devices have a UTC format counter
-- 
2.40.1

[PATCH v3 3/9] testptp: Remove magic numbers related to nanosecond to second conversion

[Rahul Rameshbabu]

Use existing NSEC_PER_SEC declaration in place of hardcoded magic numbers.

Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Shuah Khan <shuah@kernel.org>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Maciek Machnikowski <maciek@machnikowski.net>
Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Acked-by: Richard Cochran <richardcochran@gmail.com>
---
 tools/testing/selftests/ptp/testptp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/ptp/testptp.c b/tools/testing/selftests/ptp/testptp.c
index 198ad5f32187..ca2b03d57aef 100644
--- a/tools/testing/selftests/ptp/testptp.c
+++ b/tools/testing/selftests/ptp/testptp.c
@@ -110,7 +110,7 @@ static long ppb_to_scaled_ppm(int ppb)
 
 static int64_t pctns(struct ptp_clock_time *t)
 {
-	return t->sec * 1000000000LL + t->nsec;
+	return t->sec * NSEC_PER_SEC + t->nsec;
 }
 
 static void usage(char *progname)
@@ -317,7 +317,7 @@ int main(int argc, char *argv[])
 		tx.time.tv_usec = adjns;
 		while (tx.time.tv_usec < 0) {
 			tx.time.tv_sec  -= 1;
-			tx.time.tv_usec += 1000000000;
+			tx.time.tv_usec += NSEC_PER_SEC;
 		}
 
 		if (clock_adjtime(clkid, &tx) < 0) {
-- 
2.40.1

[PATCH v3 4/9] testptp: Add support for testing ptp_clock_info .adjphase callback

[Rahul Rameshbabu]

Invoke clock_adjtime syscall with tx.modes set with ADJ_OFFSET when testptp
is invoked with a phase adjustment offset value. Support seconds and
nanoseconds for the offset value.

Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Shuah Khan <shuah@kernel.org>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Maciek Machnikowski <maciek@machnikowski.net>
Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Acked-by: Richard Cochran <richardcochran@gmail.com>
---
 tools/testing/selftests/ptp/testptp.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/tools/testing/selftests/ptp/testptp.c b/tools/testing/selftests/ptp/testptp.c
index ca2b03d57aef..ae23ef51f198 100644
--- a/tools/testing/selftests/ptp/testptp.c
+++ b/tools/testing/selftests/ptp/testptp.c
@@ -134,6 +134,7 @@ static void usage(char *progname)
 		"            1 - external time stamp\n"
 		"            2 - periodic output\n"
 		" -n val     shift the ptp clock time by 'val' nanoseconds\n"
+		" -o val     phase offset (in nanoseconds) to be provided to the PHC servo\n"
 		" -p val     enable output with a period of 'val' nanoseconds\n"
 		" -H val     set output phase to 'val' nanoseconds (requires -p)\n"
 		" -w val     set output pulse width to 'val' nanoseconds (requires -p)\n"
@@ -167,6 +168,7 @@ int main(int argc, char *argv[])
 	int adjfreq = 0x7fffffff;
 	int adjtime = 0;
 	int adjns = 0;
+	int adjphase = 0;
 	int capabilities = 0;
 	int extts = 0;
 	int flagtest = 0;
@@ -188,7 +190,7 @@ int main(int argc, char *argv[])
 
 	progname = strrchr(argv[0], '/');
 	progname = progname ? 1+progname : argv[0];
-	while (EOF != (c = getopt(argc, argv, "cd:e:f:ghH:i:k:lL:n:p:P:sSt:T:w:z"))) {
+	while (EOF != (c = getopt(argc, argv, "cd:e:f:ghH:i:k:lL:n:o:p:P:sSt:T:w:z"))) {
 		switch (c) {
 		case 'c':
 			capabilities = 1;
@@ -228,6 +230,9 @@ int main(int argc, char *argv[])
 		case 'n':
 			adjns = atoi(optarg);
 			break;
+		case 'o':
+			adjphase = atoi(optarg);
+			break;
 		case 'p':
 			perout = atoll(optarg);
 			break;
@@ -327,6 +332,18 @@ int main(int argc, char *argv[])
 		}
 	}
 
+	if (adjphase) {
+		memset(&tx, 0, sizeof(tx));
+		tx.modes = ADJ_OFFSET | ADJ_NANO;
+		tx.offset = adjphase;
+
+		if (clock_adjtime(clkid, &tx) < 0) {
+			perror("clock_adjtime");
+		} else {
+			puts("phase adjustment okay");
+		}
+	}
+
 	if (gettime) {
 		if (clock_gettime(clkid, &ts)) {
 			perror("clock_gettime");
-- 
2.40.1

[PATCH v3 5/9] ptp: Add .getmaxphase callback to ptp_clock_info

[Rahul Rameshbabu]

Enables advertisement of the maximum offset supported by the phase control
functionality of PHCs. The callback is used to return an error if an offset
not supported by the PHC is used in ADJ_OFFSET. The ioctls
PTP_CLOCK_GETCAPS and PTP_CLOCK_GETCAPS2 now advertise the maximum offset a
PHC's phase control functionality is capable of supporting. Introduce new
sysfs node, max_phase_adjustment.

Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Shuah Khan <shuah@kernel.org>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Maciek Machnikowski <maciek@machnikowski.net>
Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Acked-by: Richard Cochran <richardcochran@gmail.com>
---

Notes:
    Changes:
    
      v2->v1:
        * Removes a macro introduced in v1 for adding PTP sysfs device
          attribute nodes using a callback for populating the data.

 drivers/ptp/ptp_chardev.c             |  5 ++++-
 drivers/ptp/ptp_clock.c               |  4 ++++
 drivers/ptp/ptp_sysfs.c               | 12 ++++++++++++
 include/linux/ptp_clock_kernel.h      |  5 +++++
 include/uapi/linux/ptp_clock.h        |  3 ++-
 tools/testing/selftests/ptp/testptp.c |  6 ++++--
 6 files changed, 31 insertions(+), 4 deletions(-)

diff --git a/drivers/ptp/ptp_chardev.c b/drivers/ptp/ptp_chardev.c
index af3bc65c4595..362bf756e6b7 100644
--- a/drivers/ptp/ptp_chardev.c
+++ b/drivers/ptp/ptp_chardev.c
@@ -136,7 +136,10 @@ long ptp_ioctl(struct posix_clock *pc, unsigned int cmd, unsigned long arg)
 		caps.pps = ptp->info->pps;
 		caps.n_pins = ptp->info->n_pins;
 		caps.cross_timestamping = ptp->info->getcrosststamp != NULL;
-		caps.adjust_phase = ptp->info->adjphase != NULL;
+		caps.adjust_phase = ptp->info->adjphase != NULL &&
+				    ptp->info->getmaxphase != NULL;
+		if (caps.adjust_phase)
+			caps.max_phase_adj = ptp->info->getmaxphase(ptp->info);
 		if (copy_to_user((void __user *)arg, &caps, sizeof(caps)))
 			err = -EFAULT;
 		break;
diff --git a/drivers/ptp/ptp_clock.c b/drivers/ptp/ptp_clock.c
index 790f9250b381..80f74e38c2da 100644
--- a/drivers/ptp/ptp_clock.c
+++ b/drivers/ptp/ptp_clock.c
@@ -135,11 +135,15 @@ static int ptp_clock_adjtime(struct posix_clock *pc, struct __kernel_timex *tx)
 		ptp->dialed_frequency = tx->freq;
 	} else if (tx->modes & ADJ_OFFSET) {
 		if (ops->adjphase) {
+			s32 max_phase_adj = ops->getmaxphase(ops);
 			s32 offset = tx->offset;
 
 			if (!(tx->modes & ADJ_NANO))
 				offset *= NSEC_PER_USEC;
 
+			if (offset > max_phase_adj || offset < -max_phase_adj)
+				return -ERANGE;
+
 			err = ops->adjphase(ops, offset);
 		}
 	} else if (tx->modes == 0) {
diff --git a/drivers/ptp/ptp_sysfs.c b/drivers/ptp/ptp_sysfs.c
index f30b0a439470..77219cdcd683 100644
--- a/drivers/ptp/ptp_sysfs.c
+++ b/drivers/ptp/ptp_sysfs.c
@@ -18,6 +18,17 @@ static ssize_t clock_name_show(struct device *dev,
 }
 static DEVICE_ATTR_RO(clock_name);
 
+static ssize_t max_phase_adjustment_show(struct device *dev,
+					 struct device_attribute *attr,
+					 char *page)
+{
+	struct ptp_clock *ptp = dev_get_drvdata(dev);
+
+	return snprintf(page, PAGE_SIZE - 1, "%d\n",
+			ptp->info->getmaxphase(ptp->info));
+}
+static DEVICE_ATTR_RO(max_phase_adjustment);
+
 #define PTP_SHOW_INT(name, var)						\
 static ssize_t var##_show(struct device *dev,				\
 			   struct device_attribute *attr, char *page)	\
@@ -309,6 +320,7 @@ static struct attribute *ptp_attrs[] = {
 	&dev_attr_clock_name.attr,
 
 	&dev_attr_max_adjustment.attr,
+	&dev_attr_max_phase_adjustment.attr,
 	&dev_attr_n_alarms.attr,
 	&dev_attr_n_external_timestamps.attr,
 	&dev_attr_n_periodic_outputs.attr,
diff --git a/include/linux/ptp_clock_kernel.h b/include/linux/ptp_clock_kernel.h
index f8e8443a8b35..1ef4e0f9bd2a 100644
--- a/include/linux/ptp_clock_kernel.h
+++ b/include/linux/ptp_clock_kernel.h
@@ -82,6 +82,10 @@ struct ptp_system_timestamp {
  *             parameter delta: PHC servo phase adjustment target
  *                              in nanoseconds.
  *
+ * @getmaxphase:  Advertises maximum offset that can be provided
+ *                to the hardware clock's phase control functionality
+ *                through adjphase.
+ *
  * @adjtime:  Shifts the time of the hardware clock.
  *            parameter delta: Desired change in nanoseconds.
  *
@@ -171,6 +175,7 @@ struct ptp_clock_info {
 	struct ptp_pin_desc *pin_config;
 	int (*adjfine)(struct ptp_clock_info *ptp, long scaled_ppm);
 	int (*adjphase)(struct ptp_clock_info *ptp, s32 phase);
+	s32 (*getmaxphase)(struct ptp_clock_info *ptp);
 	int (*adjtime)(struct ptp_clock_info *ptp, s64 delta);
 	int (*gettime64)(struct ptp_clock_info *ptp, struct timespec64 *ts);
 	int (*gettimex64)(struct ptp_clock_info *ptp, struct timespec64 *ts,
diff --git a/include/uapi/linux/ptp_clock.h b/include/uapi/linux/ptp_clock.h
index 1d108d597f66..05cc35fc94ac 100644
--- a/include/uapi/linux/ptp_clock.h
+++ b/include/uapi/linux/ptp_clock.h
@@ -95,7 +95,8 @@ struct ptp_clock_caps {
 	int cross_timestamping;
 	/* Whether the clock supports adjust phase */
 	int adjust_phase;
-	int rsv[12];   /* Reserved for future use. */
+	int max_phase_adj; /* Maximum phase adjustment in nanoseconds. */
+	int rsv[11];       /* Reserved for future use. */
 };
 
 struct ptp_extts_request {
diff --git a/tools/testing/selftests/ptp/testptp.c b/tools/testing/selftests/ptp/testptp.c
index ae23ef51f198..a162a3e15c29 100644
--- a/tools/testing/selftests/ptp/testptp.c
+++ b/tools/testing/selftests/ptp/testptp.c
@@ -292,7 +292,8 @@ int main(int argc, char *argv[])
 			       "  %d pulse per second\n"
 			       "  %d programmable pins\n"
 			       "  %d cross timestamping\n"
-			       "  %d adjust_phase\n",
+			       "  %d adjust_phase\n"
+			       "  %d maximum phase adjustment (ns)\n",
 			       caps.max_adj,
 			       caps.n_alarm,
 			       caps.n_ext_ts,
@@ -300,7 +301,8 @@ int main(int argc, char *argv[])
 			       caps.pps,
 			       caps.n_pins,
 			       caps.cross_timestamping,
-			       caps.adjust_phase);
+			       caps.adjust_phase,
+			       caps.max_phase_adj);
 		}
 	}
 
-- 
2.40.1

Re: [PATCH v3 5/9] ptp: Add .getmaxphase callback to ptp_clock_info

[Nathan Chancellor]

Hi Rahul,

On Mon, Jun 12, 2023 at 02:14:56PM -0700, Rahul Rameshbabu wrote:
> Enables advertisement of the maximum offset supported by the phase control
> functionality of PHCs. The callback is used to return an error if an offset
> not supported by the PHC is used in ADJ_OFFSET. The ioctls
> PTP_CLOCK_GETCAPS and PTP_CLOCK_GETCAPS2 now advertise the maximum offset a
> PHC's phase control functionality is capable of supporting. Introduce new
> sysfs node, max_phase_adjustment.
> 
> Cc: Jakub Kicinski <kuba@kernel.org>
> Cc: Shuah Khan <shuah@kernel.org>
> Cc: Richard Cochran <richardcochran@gmail.com>
> Cc: Maciek Machnikowski <maciek@machnikowski.net>
> Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
> Acked-by: Richard Cochran <richardcochran@gmail.com>

<snip>

> diff --git a/drivers/ptp/ptp_sysfs.c b/drivers/ptp/ptp_sysfs.c
> index f30b0a439470..77219cdcd683 100644
> --- a/drivers/ptp/ptp_sysfs.c
> +++ b/drivers/ptp/ptp_sysfs.c
> @@ -18,6 +18,17 @@ static ssize_t clock_name_show(struct device *dev,
>  }
>  static DEVICE_ATTR_RO(clock_name);
>  
> +static ssize_t max_phase_adjustment_show(struct device *dev,
> +					 struct device_attribute *attr,
> +					 char *page)
> +{
> +	struct ptp_clock *ptp = dev_get_drvdata(dev);
> +
> +	return snprintf(page, PAGE_SIZE - 1, "%d\n",
> +			ptp->info->getmaxphase(ptp->info));

I am seeing a crash when accessing this sysfs node, which I initially
found by running LTP's read_all test case.

# cat /sys/class/ptp/ptp0/max_phase_adjustment
fish: Job 1, 'cat /sys/class/ptp/ptp0/max_pha…' terminated by signal SIGKILL (Forced quit)

# dmesg
[  133.104459] BUG: kernel NULL pointer dereference, address: 0000000000000000
[  133.104472] #PF: supervisor instruction fetch in kernel mode
[  133.104478] #PF: error_code(0x0010) - not-present page
[  133.104483] PGD 0 P4D 0 
[  133.104490] Oops: 0010 [#2] PREEMPT SMP NOPTI
[  133.104498] CPU: 13 PID: 2705 Comm: cat Tainted: G      D            6.4.0-rc6-debug-01344-gc3b60ab7a4df #1 d68962f26eeefb0e64d3dd104c3eef4a1ac5b0d5
[  133.104508] Hardware name: ASUS System Product Name/PRIME Z590M-PLUS, BIOS 1203 10/27/2021
[  133.104512] RIP: 0010:0x0
[  133.104563] Code: Unable to access opcode bytes at 0xffffffffffffffd6.
[  133.104567] RSP: 0018:ffffbc38c5e2fdb8 EFLAGS: 00010286
[  133.104574] RAX: 0000000000000000 RBX: ffff9e3fc8e62000 RCX: ffffffffbb386100
[  133.104579] RDX: ffff9e3fc8e62000 RSI: ffffffffbb386100 RDI: ffff9e3fc43ef968
[  133.104583] RBP: ffffffffba7795b0 R08: ffff9e3fd106c0f0 R09: ffff9e3fd10418c0
[  133.104587] R10: ffff9e3fc8e62000 R11: 0000000000000000 R12: ffffbc38c5e2fe88
[  133.104590] R13: ffffbc38c5e2fe60 R14: 0000000000000001 R15: ffffbc38c5e2fef8
[  133.104594] FS:  00007f24dc5e5740(0000) GS:ffff9e46ff740000(0000) knlGS:0000000000000000
[  133.104600] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  133.104605] CR2: ffffffffffffffd6 CR3: 0000000104352001 CR4: 0000000000770ee0
[  133.104610] PKRU: 55555554
[  133.104613] Call Trace:
[  133.104617]  <TASK>
[  133.104622]  ? __die+0x23/0x70
[  133.104632]  ? page_fault_oops+0x171/0x4e0
[  133.104641]  ? exc_page_fault+0x7f/0x180
[  133.104649]  ? asm_exc_page_fault+0x26/0x30
[  133.104662]  ? seq_read_iter+0x375/0x480
[  133.104670]  max_phase_adjustment_show+0x1e/0x40
[  133.104680]  dev_attr_show+0x19/0x60
[  133.104692]  sysfs_kf_seq_show+0xa8/0x100
[  133.104703]  seq_read_iter+0x120/0x480
[  133.104711]  vfs_read+0x1f3/0x320
[  133.104721]  ksys_read+0x6f/0xf0
[  133.104730]  do_syscall_64+0x5d/0x90
[  133.104741]  entry_SYSCALL_64_after_hwframe+0x72/0xdc
[  133.104750] RIP: 0033:0x7f24dc6e1b21
[  133.104763] Code: c5 fe ff ff 50 48 8d 3d 25 7d 0a 00 e8 e8 11 02 00 0f 1f 84 00 00 00 00 00 f3 0f 1e fa 80 3d dd 99 0e 00 00 74 13 31 c0 0f 05 <48> 3d 00 f0 ff ff 77 57 c3 66 0f 1f 44 00 00 48 83 ec 28 48 89 54
[  133.104769] RSP: 002b:00007ffea4af1b88 EFLAGS: 00000246 ORIG_RAX: 0000000000000000
[  133.104776] RAX: ffffffffffffffda RBX: 0000000000020000 RCX: 00007f24dc6e1b21
[  133.104780] RDX: 0000000000020000 RSI: 00007f24dc5c4000 RDI: 0000000000000003
[  133.104784] RBP: 0000000000020000 R08: 00000000ffffffff R09: 0000000000000000
[  133.104788] R10: 0000000000000022 R11: 0000000000000246 R12: 00007f24dc5c4000
[  133.104792] R13: 0000000000000003 R14: 0000000000020000 R15: 0000000000000000
[  133.104799]  </TASK>
[  133.104801] Modules linked in: overlay xt_mark snd_seq_dummy snd_hrtimer snd_seq snd_seq_device tun hid_logitech_hidpp mousedev joydev xt_CHECKSUM xt_MASQUERADE xt_conntrack ipt_REJECT nf_reject_ipv4 xt_tcpudp nft_compat nft_chain_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 nf_tables nfnetlink bridge stp llc hid_logitech_dj hid_razer snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic vfat fat snd_sof_pci_intel_tgl snd_sof_intel_hda_common snd_soc_hdac_hda snd_sof_pci snd_sof_xtensa_dsp snd_sof_intel_hda_mlink intel_rapl_msr snd_sof_intel_hda intel_rapl_common i915 snd_sof snd_sof_utils snd_hda_ext_core x86_pkg_temp_thermal snd_soc_acpi_intel_match intel_powerclamp snd_soc_acpi coretemp snd_soc_core kvm_intel i2c_algo_bit snd_compress drm_buddy snd_hda_intel kvm snd_intel_dspcfg eeepc_wmi intel_gtt irqbypass crct10dif_pclmul drm_display_helper crc32_pclmul snd_hda_codec asus_wmi polyval_clmulni mei_hdcp polyval_generic snd_hwdep ledtrig_audio mei_pxp iTCO_wdt gf128mul drm_kms_helper
[  133.104921]  ghash_clmulni_intel sparse_keymap intel_pmc_bxt snd_hda_core sha512_ssse3 syscopyarea platform_profile iTCO_vendor_support rfkill ee1004 aesni_intel wmi_bmof crypto_simd cryptd snd_pcm sysfillrect intel_cstate sysimgblt mei_me snd_timer spi_nor intel_uncore i2c_i801 e1000e snd intel_lpss_pci cec mtd pcspkr mei intel_lpss soundcore i2c_smbus ttm idma64 video wmi acpi_tad acpi_pad usbhid mac_hid pkcs8_key_parser dm_multipath drm crypto_user fuse dm_mod loop zram bpf_preload ip_tables x_tables nvme spi_intel_pci nvme_core xhci_pci spi_intel xhci_pci_renesas nvme_common btrfs blake2b_generic libcrc32c crc32c_generic crc32c_intel xor raid6_pq
[  133.105024] CR2: 0000000000000000
[  133.105029] ---[ end trace 0000000000000000 ]---
[  133.105033] RIP: 0010:0x0
[  133.105046] Code: Unable to access opcode bytes at 0xffffffffffffffd6.
[  133.105049] RSP: 0018:ffffbc38c5aafce0 EFLAGS: 00010286
[  133.105054] RAX: 0000000000000000 RBX: ffff9e3ffdfe5000 RCX: ffffffffbb386100
[  133.105058] RDX: ffff9e3ffdfe5000 RSI: ffffffffbb386100 RDI: ffff9e3fc43ef968
[  133.105062] RBP: ffffffffba7795b0 R08: ffff9e3fd106c0f0 R09: ffff9e3fc4d8fc80
[  133.105065] R10: ffff9e3ffdfe5000 R11: 0000000000000000 R12: ffffbc38c5aafdb0
[  133.105069] R13: ffffbc38c5aafd88 R14: 0000000000000001 R15: ffffbc38c5aafe20
[  133.105072] FS:  00007f24dc5e5740(0000) GS:ffff9e46ff740000(0000) knlGS:0000000000000000
[  133.105077] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  133.105081] CR2: ffffffffffffffd6 CR3: 0000000104352001 CR4: 0000000000770ee0
[  133.105085] PKRU: 55555554
[  133.105088] note: cat[2705] exited with irqs disabled

This was also reported at [1], I apologize for the duplicate report but
it does not seem like there has been any movement on this from what I
can tell.

If there is any additional information I can provide or patches I can
test, please let me know.

> +}
> +static DEVICE_ATTR_RO(max_phase_adjustment);
> +
>  #define PTP_SHOW_INT(name, var)						\
>  static ssize_t var##_show(struct device *dev,				\
>  			   struct device_attribute *attr, char *page)	\
> @@ -309,6 +320,7 @@ static struct attribute *ptp_attrs[] = {
>  	&dev_attr_clock_name.attr,
>  
>  	&dev_attr_max_adjustment.attr,
> +	&dev_attr_max_phase_adjustment.attr,
>  	&dev_attr_n_alarms.attr,
>  	&dev_attr_n_external_timestamps.attr,
>  	&dev_attr_n_periodic_outputs.attr,

[1]: https://lore.kernel.org/89dfc918-9757-4487-aa72-615f7029f6c1@app.fastmail.com/

Cheers,
Nathan

Re: [PATCH v3 5/9] ptp: Add .getmaxphase callback to ptp_clock_info

[Rahul Rameshbabu]

On Tue, 27 Jun, 2023 09:21:46 -0700 Nathan Chancellor <nathan@kernel.org> wrote:
> Hi Rahul,
>
> On Mon, Jun 12, 2023 at 02:14:56PM -0700, Rahul Rameshbabu wrote:
>> Enables advertisement of the maximum offset supported by the phase control
>> functionality of PHCs. The callback is used to return an error if an offset
>> not supported by the PHC is used in ADJ_OFFSET. The ioctls
>> PTP_CLOCK_GETCAPS and PTP_CLOCK_GETCAPS2 now advertise the maximum offset a
>> PHC's phase control functionality is capable of supporting. Introduce new
>> sysfs node, max_phase_adjustment.
>> 
>> Cc: Jakub Kicinski <kuba@kernel.org>
>> Cc: Shuah Khan <shuah@kernel.org>
>> Cc: Richard Cochran <richardcochran@gmail.com>
>> Cc: Maciek Machnikowski <maciek@machnikowski.net>
>> Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
>> Acked-by: Richard Cochran <richardcochran@gmail.com>
>
> <snip>
>
>> diff --git a/drivers/ptp/ptp_sysfs.c b/drivers/ptp/ptp_sysfs.c
>> index f30b0a439470..77219cdcd683 100644
>> --- a/drivers/ptp/ptp_sysfs.c
>> +++ b/drivers/ptp/ptp_sysfs.c
>> @@ -18,6 +18,17 @@ static ssize_t clock_name_show(struct device *dev,
>>  }
>>  static DEVICE_ATTR_RO(clock_name);
>>  
>> +static ssize_t max_phase_adjustment_show(struct device *dev,
>> +					 struct device_attribute *attr,
>> +					 char *page)
>> +{
>> +	struct ptp_clock *ptp = dev_get_drvdata(dev);
>> +
>> +	return snprintf(page, PAGE_SIZE - 1, "%d\n",
>> +			ptp->info->getmaxphase(ptp->info));
>
> I am seeing a crash when accessing this sysfs node, which I initially
> found by running LTP's read_all test case.
>
> # cat /sys/class/ptp/ptp0/max_phase_adjustment
> fish: Job 1, 'cat /sys/class/ptp/ptp0/max_pha…' terminated by signal SIGKILL (Forced quit)
>
> # dmesg
> [  133.104459] BUG: kernel NULL pointer dereference, address: 0000000000000000
> [  133.104472] #PF: supervisor instruction fetch in kernel mode
> [  133.104478] #PF: error_code(0x0010) - not-present page
> [  133.104483] PGD 0 P4D 0 
> [  133.104490] Oops: 0010 [#2] PREEMPT SMP NOPTI
> [  133.104498] CPU: 13 PID: 2705 Comm: cat Tainted: G      D            6.4.0-rc6-debug-01344-gc3b60ab7a4df #1 d68962f26eeefb0e64d3dd104c3eef4a1ac5b0d5
> [  133.104508] Hardware name: ASUS System Product Name/PRIME Z590M-PLUS, BIOS 1203 10/27/2021
> [  133.104512] RIP: 0010:0x0
> [  133.104563] Code: Unable to access opcode bytes at 0xffffffffffffffd6.
> [  133.104567] RSP: 0018:ffffbc38c5e2fdb8 EFLAGS: 00010286
> [  133.104574] RAX: 0000000000000000 RBX: ffff9e3fc8e62000 RCX: ffffffffbb386100
> [  133.104579] RDX: ffff9e3fc8e62000 RSI: ffffffffbb386100 RDI: ffff9e3fc43ef968
> [  133.104583] RBP: ffffffffba7795b0 R08: ffff9e3fd106c0f0 R09: ffff9e3fd10418c0
> [  133.104587] R10: ffff9e3fc8e62000 R11: 0000000000000000 R12: ffffbc38c5e2fe88
> [  133.104590] R13: ffffbc38c5e2fe60 R14: 0000000000000001 R15: ffffbc38c5e2fef8
> [  133.104594] FS:  00007f24dc5e5740(0000) GS:ffff9e46ff740000(0000) knlGS:0000000000000000
> [  133.104600] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [  133.104605] CR2: ffffffffffffffd6 CR3: 0000000104352001 CR4: 0000000000770ee0
> [  133.104610] PKRU: 55555554
> [  133.104613] Call Trace:
> [  133.104617]  <TASK>
> [  133.104622]  ? __die+0x23/0x70
> [  133.104632]  ? page_fault_oops+0x171/0x4e0
> [  133.104641]  ? exc_page_fault+0x7f/0x180
> [  133.104649]  ? asm_exc_page_fault+0x26/0x30
> [  133.104662]  ? seq_read_iter+0x375/0x480
> [  133.104670]  max_phase_adjustment_show+0x1e/0x40
> [  133.104680]  dev_attr_show+0x19/0x60
> [  133.104692]  sysfs_kf_seq_show+0xa8/0x100
> [  133.104703]  seq_read_iter+0x120/0x480
> [  133.104711]  vfs_read+0x1f3/0x320
> [  133.104721]  ksys_read+0x6f/0xf0
> [  133.104730]  do_syscall_64+0x5d/0x90
> [  133.104741]  entry_SYSCALL_64_after_hwframe+0x72/0xdc
> [  133.104750] RIP: 0033:0x7f24dc6e1b21
> [  133.104763] Code: c5 fe ff ff 50 48 8d 3d 25 7d 0a 00 e8 e8 11 02 00 0f 1f 84 00 00 00 00 00 f3 0f 1e fa 80 3d dd 99 0e 00 00 74 13 31 c0 0f 05 <48> 3d 00 f0 ff ff 77 57 c3 66 0f 1f 44 00 00 48 83 ec 28 48 89 54
> [  133.104769] RSP: 002b:00007ffea4af1b88 EFLAGS: 00000246 ORIG_RAX: 0000000000000000
> [  133.104776] RAX: ffffffffffffffda RBX: 0000000000020000 RCX: 00007f24dc6e1b21
> [  133.104780] RDX: 0000000000020000 RSI: 00007f24dc5c4000 RDI: 0000000000000003
> [  133.104784] RBP: 0000000000020000 R08: 00000000ffffffff R09: 0000000000000000
> [  133.104788] R10: 0000000000000022 R11: 0000000000000246 R12: 00007f24dc5c4000
> [  133.104792] R13: 0000000000000003 R14: 0000000000020000 R15: 0000000000000000
> [  133.104799]  </TASK>
> [ 133.104801] Modules linked in: overlay xt_mark snd_seq_dummy snd_hrtimer
> snd_seq snd_seq_device tun hid_logitech_hidpp mousedev joydev xt_CHECKSUM
> xt_MASQUERADE xt_conntrack ipt_REJECT nf_reject_ipv4 xt_tcpudp nft_compat
> nft_chain_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 nf_tables
> nfnetlink bridge stp llc hid_logitech_dj hid_razer snd_hda_codec_hdmi
> snd_hda_codec_realtek snd_hda_codec_generic vfat fat snd_sof_pci_intel_tgl
> snd_sof_intel_hda_common snd_soc_hdac_hda snd_sof_pci snd_sof_xtensa_dsp
> snd_sof_intel_hda_mlink intel_rapl_msr snd_sof_intel_hda intel_rapl_common i915
> snd_sof snd_sof_utils snd_hda_ext_core x86_pkg_temp_thermal
> snd_soc_acpi_intel_match intel_powerclamp snd_soc_acpi coretemp snd_soc_core
> kvm_intel i2c_algo_bit snd_compress drm_buddy snd_hda_intel kvm snd_intel_dspcfg
> eeepc_wmi intel_gtt irqbypass crct10dif_pclmul drm_display_helper crc32_pclmul
> snd_hda_codec asus_wmi polyval_clmulni mei_hdcp polyval_generic snd_hwdep
> ledtrig_audio mei_pxp iTCO_wdt gf128mul drm_kms_helper
> [ 133.104921] ghash_clmulni_intel sparse_keymap intel_pmc_bxt snd_hda_core
> sha512_ssse3 syscopyarea platform_profile iTCO_vendor_support rfkill ee1004
> aesni_intel wmi_bmof crypto_simd cryptd snd_pcm sysfillrect intel_cstate
> sysimgblt mei_me snd_timer spi_nor intel_uncore i2c_i801 e1000e snd
> intel_lpss_pci cec mtd pcspkr mei intel_lpss soundcore i2c_smbus ttm idma64
> video wmi acpi_tad acpi_pad usbhid mac_hid pkcs8_key_parser dm_multipath drm
> crypto_user fuse dm_mod loop zram bpf_preload ip_tables x_tables nvme
> spi_intel_pci nvme_core xhci_pci spi_intel xhci_pci_renesas nvme_common btrfs
> blake2b_generic libcrc32c crc32c_generic crc32c_intel xor raid6_pq
> [  133.105024] CR2: 0000000000000000
> [  133.105029] ---[ end trace 0000000000000000 ]---
> [  133.105033] RIP: 0010:0x0
> [  133.105046] Code: Unable to access opcode bytes at 0xffffffffffffffd6.
> [  133.105049] RSP: 0018:ffffbc38c5aafce0 EFLAGS: 00010286
> [  133.105054] RAX: 0000000000000000 RBX: ffff9e3ffdfe5000 RCX: ffffffffbb386100
> [  133.105058] RDX: ffff9e3ffdfe5000 RSI: ffffffffbb386100 RDI: ffff9e3fc43ef968
> [  133.105062] RBP: ffffffffba7795b0 R08: ffff9e3fd106c0f0 R09: ffff9e3fc4d8fc80
> [  133.105065] R10: ffff9e3ffdfe5000 R11: 0000000000000000 R12: ffffbc38c5aafdb0
> [  133.105069] R13: ffffbc38c5aafd88 R14: 0000000000000001 R15: ffffbc38c5aafe20
> [  133.105072] FS:  00007f24dc5e5740(0000) GS:ffff9e46ff740000(0000) knlGS:0000000000000000
> [  133.105077] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [  133.105081] CR2: ffffffffffffffd6 CR3: 0000000104352001 CR4: 0000000000770ee0
> [  133.105085] PKRU: 55555554
> [  133.105088] note: cat[2705] exited with irqs disabled
>
> This was also reported at [1], I apologize for the duplicate report but
> it does not seem like there has been any movement on this from what I
> can tell.
>
> If there is any additional information I can provide or patches I can
> test, please let me know.

Thanks for the detailed report. From this alone, I see the core of the
issue and will submit a fix to net today. Thanks for the additional
follow-up. Missed the LTP fs testing report.

-- Rahul Rameshbabu

>
>> +}
>> +static DEVICE_ATTR_RO(max_phase_adjustment);
>> +
>>  #define PTP_SHOW_INT(name, var)						\
>>  static ssize_t var##_show(struct device *dev,				\
>>  			   struct device_attribute *attr, char *page)	\
>> @@ -309,6 +320,7 @@ static struct attribute *ptp_attrs[] = {
>>  	&dev_attr_clock_name.attr,
>>  
>>  	&dev_attr_max_adjustment.attr,
>> +	&dev_attr_max_phase_adjustment.attr,
>>  	&dev_attr_n_alarms.attr,
>>  	&dev_attr_n_external_timestamps.attr,
>>  	&dev_attr_n_periodic_outputs.attr,
>
> [1]: https://lore.kernel.org/89dfc918-9757-4487-aa72-615f7029f6c1@app.fastmail.com/
>
> Cheers,
> Nathan

[PATCH v3 6/9] net/mlx5: Add .getmaxphase ptp_clock_info callback

[Rahul Rameshbabu]

Implement .getmaxphase callback of ptp_clock_info in mlx5 driver. No longer
do a range check in .adjphase callback implementation. Handled by the ptp
stack.

Cc: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Acked-by: Richard Cochran <richardcochran@gmail.com>
---
 .../ethernet/mellanox/mlx5/core/lib/clock.c   | 31 +++++++++----------
 1 file changed, 15 insertions(+), 16 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
index 932fbc843c69..973babfaff25 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
@@ -93,17 +93,23 @@ static bool mlx5_modify_mtutc_allowed(struct mlx5_core_dev *mdev)
 	return MLX5_CAP_MCAM_FEATURE(mdev, ptpcyc2realtime_modify);
 }
 
-static bool mlx5_is_mtutc_time_adj_cap(struct mlx5_core_dev *mdev, s64 delta)
+static s32 mlx5_ptp_getmaxphase(struct ptp_clock_info *ptp)
 {
-	s64 min = MLX5_MTUTC_OPERATION_ADJUST_TIME_MIN;
-	s64 max = MLX5_MTUTC_OPERATION_ADJUST_TIME_MAX;
+	struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
+	struct mlx5_core_dev *mdev;
 
-	if (MLX5_CAP_MCAM_FEATURE(mdev, mtutc_time_adjustment_extended_range)) {
-		min = MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MIN;
-		max = MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MAX;
-	}
+	mdev = container_of(clock, struct mlx5_core_dev, clock);
+
+	return MLX5_CAP_MCAM_FEATURE(mdev, mtutc_time_adjustment_extended_range) ?
+		       MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MAX :
+			     MLX5_MTUTC_OPERATION_ADJUST_TIME_MAX;
+}
+
+static bool mlx5_is_mtutc_time_adj_cap(struct mlx5_core_dev *mdev, s64 delta)
+{
+	s64 max = mlx5_ptp_getmaxphase(&mdev->clock.ptp_info);
 
-	if (delta < min || delta > max)
+	if (delta < -max || delta > max)
 		return false;
 
 	return true;
@@ -351,14 +357,6 @@ static int mlx5_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
 
 static int mlx5_ptp_adjphase(struct ptp_clock_info *ptp, s32 delta)
 {
-	struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
-	struct mlx5_core_dev *mdev;
-
-	mdev = container_of(clock, struct mlx5_core_dev, clock);
-
-	if (!mlx5_is_mtutc_time_adj_cap(mdev, delta))
-		return -ERANGE;
-
 	return mlx5_ptp_adjtime(ptp, delta);
 }
 
@@ -734,6 +732,7 @@ static const struct ptp_clock_info mlx5_ptp_clock_info = {
 	.pps		= 0,
 	.adjfine	= mlx5_ptp_adjfine,
 	.adjphase	= mlx5_ptp_adjphase,
+	.getmaxphase    = mlx5_ptp_getmaxphase,
 	.adjtime	= mlx5_ptp_adjtime,
 	.gettimex64	= mlx5_ptp_gettimex,
 	.settime64	= mlx5_ptp_settime,
-- 
2.40.1

[PATCH v3 7/9] ptp: ptp_clockmatrix: Add .getmaxphase ptp_clock_info callback

[Rahul Rameshbabu]

Advertise the maximum offset the .adjphase callback is capable of
supporting in nanoseconds for IDT ClockMatrix devices. Depend on
ptp_clock_adjtime for handling out-of-range offsets. ptp_clock_adjtime
returns -ERANGE instead of clamping out-of-range offsets.

Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Vincent Cheng <vincent.cheng.xh@renesas.com>
Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
---

Notes:
    Changes:
    
      v3->v2:
        * Add information about returning -ERANGE instead of clamping
          out-of-range offsets.
    
          Link: https://lore.kernel.org/netdev/13b7315446390d3a78d8f508937354f12778b68e.camel@redhat.com/

 drivers/ptp/ptp_clockmatrix.c | 36 +++++++++++++++++------------------
 drivers/ptp/ptp_clockmatrix.h |  2 +-
 2 files changed, 18 insertions(+), 20 deletions(-)

diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c
index c9d451bf89e2..f6f9d4adce04 100644
--- a/drivers/ptp/ptp_clockmatrix.c
+++ b/drivers/ptp/ptp_clockmatrix.c
@@ -1692,14 +1692,23 @@ static int initialize_dco_operating_mode(struct idtcm_channel *channel)
 /* PTP Hardware Clock interface */
 
 /*
- * Maximum absolute value for write phase offset in picoseconds
- *
- * @channel:  channel
- * @delta_ns: delta in nanoseconds
+ * Maximum absolute value for write phase offset in nanoseconds
  *
  * Destination signed register is 32-bit register in resolution of 50ps
  *
- * 0x7fffffff * 50 =  2147483647 * 50 = 107374182350
+ * 0x7fffffff * 50 =  2147483647 * 50 = 107374182350 ps
+ * Represent 107374182350 ps as 107374182 ns
+ */
+static s32 idtcm_getmaxphase(struct ptp_clock_info *ptp __always_unused)
+{
+	return MAX_ABS_WRITE_PHASE_NANOSECONDS;
+}
+
+/*
+ * Internal function for implementing support for write phase offset
+ *
+ * @channel:  channel
+ * @delta_ns: delta in nanoseconds
  */
 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
 {
@@ -1708,7 +1717,6 @@ static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
 	u8 i;
 	u8 buf[4] = {0};
 	s32 phase_50ps;
-	s64 offset_ps;
 
 	if (channel->mode != PTP_PLL_MODE_WRITE_PHASE) {
 		err = channel->configure_write_phase(channel);
@@ -1716,19 +1724,7 @@ static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
 			return err;
 	}
 
-	offset_ps = (s64)delta_ns * 1000;
-
-	/*
-	 * Check for 32-bit signed max * 50:
-	 *
-	 * 0x7fffffff * 50 =  2147483647 * 50 = 107374182350
-	 */
-	if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
-		offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
-	else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
-		offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
-
-	phase_50ps = div_s64(offset_ps, 50);
+	phase_50ps = div_s64((s64)delta_ns * 1000, 50);
 
 	for (i = 0; i < 4; i++) {
 		buf[i] = phase_50ps & 0xff;
@@ -2048,6 +2044,7 @@ static const struct ptp_clock_info idtcm_caps = {
 	.n_ext_ts	= MAX_TOD,
 	.n_pins		= MAX_REF_CLK,
 	.adjphase	= &idtcm_adjphase,
+	.getmaxphase	= &idtcm_getmaxphase,
 	.adjfine	= &idtcm_adjfine,
 	.adjtime	= &idtcm_adjtime,
 	.gettime64	= &idtcm_gettime,
@@ -2064,6 +2061,7 @@ static const struct ptp_clock_info idtcm_caps_deprecated = {
 	.n_ext_ts	= MAX_TOD,
 	.n_pins		= MAX_REF_CLK,
 	.adjphase	= &idtcm_adjphase,
+	.getmaxphase    = &idtcm_getmaxphase,
 	.adjfine	= &idtcm_adjfine,
 	.adjtime	= &idtcm_adjtime_deprecated,
 	.gettime64	= &idtcm_gettime,
diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h
index bf1e49409844..7c17c4f7f573 100644
--- a/drivers/ptp/ptp_clockmatrix.h
+++ b/drivers/ptp/ptp_clockmatrix.h
@@ -18,7 +18,7 @@
 #define MAX_PLL		(8)
 #define MAX_REF_CLK	(16)
 
-#define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)
+#define MAX_ABS_WRITE_PHASE_NANOSECONDS (107374182L)
 
 #define TOD_MASK_ADDR		(0xFFA5)
 #define DEFAULT_TOD_MASK	(0x04)
-- 
2.40.1

[PATCH v3 8/9] ptp: idt82p33: Add .getmaxphase ptp_clock_info callback

[Rahul Rameshbabu]

Advertise the maximum offset the .adjphase callback is capable of
supporting in nanoseconds for IDT devices.

Refactor the negation of the offset stored in the register to be after the
boundary check of the offset value rather than before. Boundary check based
on the intended value rather than its device-specific representation.
Depend on ptp_clock_adjtime for handling out-of-range offsets.
ptp_clock_adjtime returns -ERANGE instead of clamping out-of-range offsets.

Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Min Li <min.li.xe@renesas.com>
Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
---

Notes:
    Changes:
    
      v3->v2:
        * Add information about returning -ERANGE instead of clamping
          out-of-range offsets.
    
          Link: https://lore.kernel.org/netdev/13b7315446390d3a78d8f508937354f12778b68e.camel@redhat.com/

 drivers/ptp/ptp_idt82p33.c | 18 +++++++++---------
 drivers/ptp/ptp_idt82p33.h |  4 ++--
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/ptp/ptp_idt82p33.c b/drivers/ptp/ptp_idt82p33.c
index afc76c22271a..057190b9cd3d 100644
--- a/drivers/ptp/ptp_idt82p33.c
+++ b/drivers/ptp/ptp_idt82p33.c
@@ -978,24 +978,23 @@ static int idt82p33_enable(struct ptp_clock_info *ptp,
 	return err;
 }
 
+static s32 idt82p33_getmaxphase(__always_unused struct ptp_clock_info *ptp)
+{
+	return WRITE_PHASE_OFFSET_LIMIT;
+}
+
 static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 offset_ns)
 {
 	struct idt82p33_channel *channel =
 		container_of(ptp, struct idt82p33_channel, caps);
 	struct idt82p33 *idt82p33 = channel->idt82p33;
-	s64 offset_regval, offset_fs;
+	s64 offset_regval;
 	u8 val[4] = {0};
 	int err;
 
-	offset_fs = (s64)(-offset_ns) * 1000000;
-
-	if (offset_fs > WRITE_PHASE_OFFSET_LIMIT)
-		offset_fs = WRITE_PHASE_OFFSET_LIMIT;
-	else if (offset_fs < -WRITE_PHASE_OFFSET_LIMIT)
-		offset_fs = -WRITE_PHASE_OFFSET_LIMIT;
-
 	/* Convert from phaseoffset_fs to register value */
-	offset_regval = div_s64(offset_fs * 1000, IDT_T0DPLL_PHASE_RESOL);
+	offset_regval = div_s64((s64)(-offset_ns) * 1000000000ll,
+				IDT_T0DPLL_PHASE_RESOL);
 
 	val[0] = offset_regval & 0xFF;
 	val[1] = (offset_regval >> 8) & 0xFF;
@@ -1175,6 +1174,7 @@ static void idt82p33_caps_init(u32 index, struct ptp_clock_info *caps,
 	caps->n_ext_ts = MAX_PHC_PLL,
 	caps->n_pins = max_pins,
 	caps->adjphase = idt82p33_adjwritephase,
+	caps->getmaxphase = idt82p33_getmaxphase,
 	caps->adjfine = idt82p33_adjfine;
 	caps->adjtime = idt82p33_adjtime;
 	caps->gettime64 = idt82p33_gettime;
diff --git a/drivers/ptp/ptp_idt82p33.h b/drivers/ptp/ptp_idt82p33.h
index 8fcb0b17d207..6a63c14b6966 100644
--- a/drivers/ptp/ptp_idt82p33.h
+++ b/drivers/ptp/ptp_idt82p33.h
@@ -43,9 +43,9 @@
 #define DEFAULT_OUTPUT_MASK_PLL1	DEFAULT_OUTPUT_MASK_PLL0
 
 /**
- * @brief Maximum absolute value for write phase offset in femtoseconds
+ * @brief Maximum absolute value for write phase offset in nanoseconds
  */
-#define WRITE_PHASE_OFFSET_LIMIT (20000052084ll)
+#define WRITE_PHASE_OFFSET_LIMIT (20000l)
 
 /** @brief Phase offset resolution
  *
-- 
2.40.1

[PATCH v3 9/9] ptp: ocp: Add .getmaxphase ptp_clock_info callback

[Rahul Rameshbabu]

Add a function that advertises a maximum offset of zero supported by
ptp_clock_info .adjphase in the OCP null ptp implementation.

Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Jonathan Lemon <jonathan.lemon@gmail.com>
Cc: Vadim Fedorenko <vadim.fedorenko@linux.dev>
Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Acked-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>
---
 drivers/ptp/ptp_ocp.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/ptp/ptp_ocp.c b/drivers/ptp/ptp_ocp.c
index ab8cab4d1560..20a974ced8d6 100644
--- a/drivers/ptp/ptp_ocp.c
+++ b/drivers/ptp/ptp_ocp.c
@@ -1124,6 +1124,12 @@ ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
 	return -EOPNOTSUPP;
 }
 
+static s32
+ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info)
+{
+	return 0;
+}
+
 static int
 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
 {
@@ -1239,6 +1245,7 @@ static const struct ptp_clock_info ptp_ocp_clock_info = {
 	.adjtime	= ptp_ocp_adjtime,
 	.adjfine	= ptp_ocp_null_adjfine,
 	.adjphase	= ptp_ocp_null_adjphase,
+	.getmaxphase	= ptp_ocp_null_getmaxphase,
 	.enable		= ptp_ocp_enable,
 	.verify		= ptp_ocp_verify,
 	.pps		= true,
-- 
2.40.1

Re: [PATCH v3 0/9] ptp .adjphase cleanups

[Rahul Rameshbabu]

On Mon, 12 Jun, 2023 14:14:51 -0700 Rahul Rameshbabu <rrameshbabu@nvidia.com> wrote:
> The goal of this patch series is to improve documentation of .adjphase, add
> a new callback .getmaxphase to enable advertising the max phase offset a
> device PHC can support, and support invoking .adjphase from the testptp
> kselftest.
>
> Changes:
>   v3->v2:
>     * Add information about returning -ERANGE instead of clamping
>       out-of-range offsets for driver implementations of .adjphase that
>       previously clamped out-of-range offsets.
>
>       Link: https://lore.kernel.org/netdev/13b7315446390d3a78d8f508937354f12778b68e.camel@redhat.com/
>   v2->v1:
>     * Removes arbitrary rule that the PHC servo must restore the frequency
>       to the value used in the last .adjfine call if any other PHC
>       operation is used after a .adjphase operation.
>     * Removes a macro introduced in v1 for adding PTP sysfs device
>       attribute nodes using a callback for populating the data.
>
> Link: https://lore.kernel.org/netdev/20230523205440.326934-1-rrameshbabu@nvidia.com/ 
> Link: https://lore.kernel.org/netdev/20230510205306.136766-1-rrameshbabu@nvidia.com/
> Link: https://lore.kernel.org/netdev/20230120160609.19160723@kernel.org/
>
> Cc: Jakub Kicinski <kuba@kernel.org>
> Cc: Richard Cochran <richardcochran@gmail.com>

Sorry that this submission did not correctly target the net-next tree in
the subject. I have been submitting to other subsystems and forgot to
target the correct tree in the subject of this patch series.

-- Rahul Rameshbabu

Re: [PATCH v3 0/9] ptp .adjphase cleanups

[patchwork-bot+netdevbpf]

Hello:

This series was applied to netdev/net-next.git (main)
by David S. Miller <davem@davemloft.net>:

On Mon, 12 Jun 2023 14:14:51 -0700 you wrote:
> The goal of this patch series is to improve documentation of .adjphase, add
> a new callback .getmaxphase to enable advertising the max phase offset a
> device PHC can support, and support invoking .adjphase from the testptp
> kselftest.
> 
> Changes:
>   v3->v2:
>     * Add information about returning -ERANGE instead of clamping
>       out-of-range offsets for driver implementations of .adjphase that
>       previously clamped out-of-range offsets.
> 
> [...]

Here is the summary with links:
  - [v3,1/9] ptp: Clarify ptp_clock_info .adjphase expects an internal servo to be used
    https://git.kernel.org/netdev/net-next/c/a05d070a6164
  - [v3,2/9] docs: ptp.rst: Add information about NVIDIA Mellanox devices
    https://git.kernel.org/netdev/net-next/c/fe3834cd0cf7
  - [v3,3/9] testptp: Remove magic numbers related to nanosecond to second conversion
    https://git.kernel.org/netdev/net-next/c/048f6d998eac
  - [v3,4/9] testptp: Add support for testing ptp_clock_info .adjphase callback
    https://git.kernel.org/netdev/net-next/c/3a9a9a613928
  - [v3,5/9] ptp: Add .getmaxphase callback to ptp_clock_info
    https://git.kernel.org/netdev/net-next/c/c3b60ab7a4df
  - [v3,6/9] net/mlx5: Add .getmaxphase ptp_clock_info callback
    https://git.kernel.org/netdev/net-next/c/67ac72a599d8
  - [v3,7/9] ptp: ptp_clockmatrix: Add .getmaxphase ptp_clock_info callback
    https://git.kernel.org/netdev/net-next/c/c066e74f34bc
  - [v3,8/9] ptp: idt82p33: Add .getmaxphase ptp_clock_info callback
    https://git.kernel.org/netdev/net-next/c/e156e4d2e43f
  - [v3,9/9] ptp: ocp: Add .getmaxphase ptp_clock_info callback
    https://git.kernel.org/netdev/net-next/c/d8ee5ca845b4

You are awesome, thank you!
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