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Miller" , Eric Dumazet , Jakub Kicinski , "Paolo Abeni" , , Ido Schimmel , Amit Cohen , Subject: Re: [PATCH net-next 2/6] mlxsw: reg: Add Management Capabilities Mask Register Date: Mon, 27 Mar 2023 11:35:24 +0200 In-Reply-To: Message-ID: <87jzz2o7hu.fsf@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT073:EE_|SN7PR12MB7934:EE_ X-MS-Office365-Filtering-Correlation-Id: a8611e5c-e5af-433d-3a5b-08db2ea79f04 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: R9KLZ92id//f3Q08rFagVpE/wHO7EKFBmt4se1cP350wFxEiYdgKc3QP6nOTro14+2HX61eNrfrZWn6btlS/AxAjbe8HH7JtKJsmaPmJRwnRe9rvINzHgoqpyLTJt22HnfKXE7K3wICWJliKGOpAVlvgJ1EWbPkNVoO/wGd1YBOW2uxQqtEKdkkM/Vi8Jm7C9gzeyE52OB16nfKHHmfR5FLKp916KjNNMgCagkC1OnL4F43IQPjom8hzLlJrHVwsZmMHDMkaeaOct40MweJWkUy5dW4r/CGmRYMLbaK0tGwhT8ICms1l8FO6MNMSHmkxDc7EsHeN5SyBEZAbXLeDe7P3FksAOx6PWQiEQcgCan9ZPEcpWCoX5rQPLP2iwKmKES5W/mRGp+Ij4nNm1PtQXtY0WOFeix/t96hLcl53Eb+vyn4aNsrAxRtO6snGppGNR1+64Jr2bSWGnQ/LLkwhL81zI2t7fA3QasDdIhsUXYEuiTwuMdqf3krHaqmaQpujX/C26wBfieu+OeMmxTOyVty3RmxcnovSz8kNziBzYm4OCAtxAaENAFkaJFO4bHzd4UPsMxuHdb7bEZWooWjHYg+6/vNuhjKvUBRfyIhfxo0hasjUWwtwy7ux8sfy9AHo/8kGHGkezZrbvwz+drlzrQKV+rsLKSK8uYvp+E/+Q8QYVRzcF9DuX/8Aa0hy7fOHAR+DIsujAVLwwcOzHqM6IjkkZsZ9f7A3XQx1jSllGOgwiI8Hen3GeeHleqjj0wyeuxcv9oXtgMVP6Y+0Q7eC8UEW+v5DGdaSBfJ1ouygOsU= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(346002)(136003)(39860400002)(396003)(376002)(451199021)(40470700004)(36840700001)(46966006)(5660300002)(316002)(70586007)(8676002)(6916009)(4326008)(107886003)(336012)(6666004)(7636003)(34020700004)(8936002)(83380400001)(26005)(36756003)(41300700001)(82310400005)(82740400003)(36860700001)(2616005)(66899021)(2906002)(70206006)(54906003)(47076005)(426003)(478600001)(356005)(86362001)(40460700003)(186003)(40480700001)(16526019);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Mar 2023 09:42:46.3921 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8611e5c-e5af-433d-3a5b-08db2ea79f04 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT073.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7934 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Simon Horman writes: > On Wed, Mar 22, 2023 at 05:49:31PM +0100, Petr Machata wrote: >> From: Amit Cohen >> >> MCAM register reports the device supported management features. Querying >> this register exposes if features are supported with the current firmware >> version in the current ASIC. Then, the drive can separate between different >> implementations dynamically. >> >> MCAM register supports querying whether a new reset flow (which includes >> PCI reset) is supported or not. Add support for the register as preparation >> for support of the new reset flow. >> >> Note that the access to the bits in the field 'mng_feature_cap_mask' is >> not same to other mask fields in other registers. In most of the cases >> bit #0 is the first one in the last dword, in MCAM register, bits #0-#31 >> are in the first dword and so on. Declare the mask field using bits arrays >> per dword to simplify the access. >> >> Signed-off-by: Amit Cohen >> Reviewed-by: Petr Machata >> Signed-off-by: Petr Machata > > I'm fine with this patch, and offered a Reviewed-by tag in another email. > But when sending that I forgot the minor nit below. > Please regard it as informational only. > >> --- >> drivers/net/ethernet/mellanox/mlxsw/reg.h | 74 +++++++++++++++++++++++ >> 1 file changed, 74 insertions(+) >> >> diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h >> index 0d7d5e28945a..c4446085ebc5 100644 >> --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h >> +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h > > ... > >> +static inline void >> +mlxsw_reg_mcam_unpack(char *payload, >> + enum mlxsw_reg_mcam_mng_feature_cap_mask_bits bit, >> + bool *p_mng_feature_cap_val) >> +{ >> + int offset = bit % (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE); >> + int dword = bit / (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE); > > nit: checkpatch seems mildly upset that there is no blank line here. Yes, thanks for pointing this out. I saw that, too. The complaint is that there should be a blank line after the declaration block, but the next line is still a part of the declaration block. >> + u8 (*getters[])(const char *, u16) = { >> + mlxsw_reg_mcam_mng_feature_cap_mask_dw0_get, >> + mlxsw_reg_mcam_mng_feature_cap_mask_dw1_get, >> + mlxsw_reg_mcam_mng_feature_cap_mask_dw2_get, >> + mlxsw_reg_mcam_mng_feature_cap_mask_dw3_get, >> + };