question on gswip_pce_table_entry_write() in lantiq_gswip_common.c

question on gswip_pce_table_entry_write() in lantiq_gswip_common.c

[Rasmus Villemoes]

Hi

Reading gswip_pce_table_entry_write() in lantiq_gswip_common.c, I'm
wondering if it really has to do all that it does. In particular, it
seems to write the same value to (a subset of) the GSWIP_PCE_TBL_CTRL
reg twice, then it reads the reg value back, manually tweaks the
remaining bits appropriately and folds in the "start access bit", then
writes the whole value to the register.

Why couldn't that be done by reading the register, do all the masking
and bit setting, then doing a single write of the whole thing?

The data sheet doesn't say anything about this complicated scheme being
necessary.

Another thing: I'd really appreciate it if someone could point me to
documentation on the various tables, i.e. what does val[2] of an entry
in GSWIP_TABLE_VLAN_MAPPING actually mean? I can see that BIT(port) is
either set or cleared from it depending on 'untagged', so I can
sort-of-guess, but I'd prefer to have it documented so I don't have to
guess. AFAICT, none of the documents I can download from MaxLinear spell
this out in any way.

Rasmus

Re: question on gswip_pce_table_entry_write() in lantiq_gswip_common.c

[Daniel Golle]

Hi Rasmus,

On Tue, Dec 23, 2025 at 09:48:26AM +0100, Rasmus Villemoes wrote:
> Hi
> 
> Reading gswip_pce_table_entry_write() in lantiq_gswip_common.c, I'm
> wondering if it really has to do all that it does. In particular, it
> seems to write the same value to (a subset of) the GSWIP_PCE_TBL_CTRL
> reg twice, then it reads the reg value back, manually tweaks the
> remaining bits appropriately and folds in the "start access bit", then
> writes the whole value to the register.

My understanding of GSWIP_PCE_TBL_CTRL is that this register is used to
set the table and address/index to used for subsequent access with the
GSWIP_PCE_TBL_* registers.

It also looks weird to me, but I didn't have much time to try to
optimize it, the sequence of register access is present since the
initial support for VLAN unaware bridge offloading

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8206e0ce96b33e6513615de9151e794bbc9f3786

> 
> Why couldn't that be done by reading the register, do all the masking
> and bit setting, then doing a single write of the whole thing?

I agree, and it looks like it could be improved in this way, the only
"special" bit there is probably GSWIP_PCE_TBL_CTRL_BAS.

> 
> The data sheet doesn't say anything about this complicated scheme being
> necessary.
> 
> Another thing: I'd really appreciate it if someone could point me to
> documentation on the various tables, i.e. what does val[2] of an entry
> in GSWIP_TABLE_VLAN_MAPPING actually mean? I can see that BIT(port) is
> either set or cleared from it depending on 'untagged', so I can
> sort-of-guess, but I'd prefer to have it documented so I don't have to
> guess. AFAICT, none of the documents I can download from MaxLinear spell
> this out in any way.

I also don't have any for-human documentation for the switch table entry
formats and registers. I doubt any documentation of that actually
exists.

Most of the switching engine itself is covered in

GSW12x_GSW14x_Register_Description_PR_Rev1.1.pdf

but also that doesn't describe the individual tables. My reference for
that is the old/proprietary SW-API driver which describes some (but not
all) of the table entry formats in code at least...

You find the SW-API as part of various GPL leaks, all files there are
under a dual BSD/GPLv2 license, so I can also share my (latest/official)
version of that driver with you in case you don't have it.


Cheers


Daniel

Re: question on gswip_pce_table_entry_write() in lantiq_gswip_common.c

[Rasmus Villemoes]

On Tue, Dec 23 2025, Daniel Golle <daniel@makrotopia.org> wrote:

>> Another thing: I'd really appreciate it if someone could point me to
>> documentation on the various tables, i.e. what does val[2] of an entry
>> in GSWIP_TABLE_VLAN_MAPPING actually mean? I can see that BIT(port) is
>> either set or cleared from it depending on 'untagged', so I can
>> sort-of-guess, but I'd prefer to have it documented so I don't have to
>> guess. AFAICT, none of the documents I can download from MaxLinear spell
>> this out in any way.
>
> I also don't have any for-human documentation for the switch table entry
> formats and registers. I doubt any documentation of that actually
> exists.
>
> Most of the switching engine itself is covered in
>
> GSW12x_GSW14x_Register_Description_PR_Rev1.1.pdf
>
> but also that doesn't describe the individual tables.

Thanks, I do have that document (with a 621442_ prefix). Amusingly, on
page 9 it says "Attention: This document is meant to be used in
conjunction with the GSWIP API documentation." But if that is supposed
to refer to 617991_Standalone_Ethernet_Switch_API_UM_PG_Rev1.2.pdf, that
doesn't really help to understand the hardware, as that only sort-of
describes the use of some library functions, the source code of which I
do not have.

> My reference for that is the old/proprietary SW-API driver which
> describes some (but not all) of the table entry formats in code at
> least...
>
> You find the SW-API as part of various GPL leaks, all files there are
> under a dual BSD/GPLv2 license, so I can also share my (latest/official)
> version of that driver with you in case you don't have it.

I have a zip file containing a
621048_GSW12x_GSW14x_Linux_DSA_Driver_V1.0_Rev1.0/ directory, and the
code in there does resemble what is in mainline somewhat. But I can't
find any more comments on the table format(s) than what is in
mainline. If you have something with just some of the tables described,
I'd very much like to have that.

Thanks,
Rasmus