From mboxrd@z Thu Jan 1 00:00:00 1970 From: NeilBrown Subject: Re: [PATCH 0/3]: net: dsa: mt7530: support MT7530 in the MT7621 SoC Date: Tue, 11 Dec 2018 16:02:00 +1100 Message-ID: <87pnu8vepj.fsf@notabene.neil.brown.name> References: <20181130075737.8041-1-gerg@kernel.org> <87r2f2pxpa.fsf@miraculix.mork.no> Mime-Version: 1.0 Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" Cc: sean.wang@mediatek.com, andrew@lunn.ch, vivien.didelot@savoirfairelinux.com, f.fainelli@gmail.com, netdev@vger.kernel.org, blogic@openwrt.org, =?utf-8?Q?Ren=C3=A9?= van Dorst To: =?utf-8?Q?Bj=C3=B8rn?= Mork , gerg@kernel.org Return-path: Received: from mx2.suse.de ([195.135.220.15]:34900 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728017AbeLKFCO (ORCPT ); Tue, 11 Dec 2018 00:02:14 -0500 In-Reply-To: <87r2f2pxpa.fsf@miraculix.mork.no> Sender: netdev-owner@vger.kernel.org List-ID: --=-=-= Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Fri, Nov 30 2018, Bj=C3=B8rn Mork wrote: > gerg@kernel.org writes: > >> I have been working towards supporting the MT7530 switch as used in the >> MediaTek MT7621 SoC. Unlike the MediaTek MT7623 the MT7621 is built arou= nd >> a dual core MIPS CPU architecture. But underneath it is what appears to >> be the same 7530 switch. > > Great! Good to see someone pushing this idea forward. > >> The following 3 patches are more of an RFC than anything. They allow >> use of the mt7530 dsa driver on this device - though with some issues >> still to resolve. The primary change required is to not use the 7623 >> specific clock and regulator setup - none of that applies when using >> the 7621 (and maybe other devices?). The other change required is to >> set the 7530 MFC register CPU port number and enable bit. >> >> The unresolved issues I still have appear to be more related to the >> MT7621 ethernet driver (drivers/staging/mt7621-eth/*). I am hoping >> someone might have some ideas on these. I don't really have any good >> documentation on the ethernet devices on the 7621, so I am kind of >> working in the dark here. > > No offense, but the mt7621-eth driver in staging is horrible. What both > Ren=C3=A9 and I have had some success with is adapting the mtk_eth_soc dr= iver > already in drivers/net/ethernet/mediatek/. Yes, I know this is supposed > to be for other SoCs, but the basic design is obviously the same. > > I have had some success with a first hackish attemt based on OpenWrt. > You can find the early tree here, but note that my focus was basically > getting one specific MT7621 board up and running: > https://github.com/bmork/LEDE/tree/mt7621-with-mainline-eth-driver > > This patch has most of the necessary changes to enable that driver for > MT7621: > https://github.com/bmork/LEDE/commit/3293bc63f5461ca1eb0bbc4ed90145335e7e= 3404 > > Not a big deal, as you can see. There is of course a reason I didn't > submit this here yet: It is by no means finished... But it works. And I > have both GMACs working with this driver, which was my primary goal. Thanks a lot for posting this. I'd be very happy to see the staging driver disappear once this is ready and in mainline. I got your patch working on 4.20-rc5 and did a performance comparison. With the staging driver (using iperf3) I get 220 MBit/sec in 680 MBit/sec out with the patched mainline driver I get 190 MBit/sec in 93 MBit/sec out (numbers are a bit rubbery, but within 10%) I haven't looked into why this might be, but thought I would mention it. Strangely when I test with scp, I get about 10MB/sec in both directions with both drivers. Maybe the CPU limits encryption speed. I have a 4.4-based kernel where I get 940MBit/sec both ways - using a precursor of the current staging driver. Thanks, NeilBrown > >> 1. TX packets are not getting an IP header checksum via the normal >> off-loaded checksumming when in DSA mode. I have to switch off >> NETIF_F_IP_CSUM, so the software stack generates the checksum. >> That checksum offloading works ok when not using the 7530 DSA driver. > > Hmm. How do I test this? > >> 2. Maximal sized RX packets get silently dropped. So receive side packets >> that are large (perfect case is the all-but-last packets in a frageme= nted >> larger packet) appear to be dropped at the mt7621 ethernet MAC level. >> The 7530 MIB switch register counters show receive packets at the phy= sical >> switch port side and at the CPU switch port - but I get no packets >> received or errors in the 7621 ethernet MAC. If I set the mtu of the >> server at the other end a little smaller (a few bytes is enough) then >> I get all the packets through. It seems like the DSA/VLAN tag bytes >> are causing a too large packet to get silently dropped somewhere. > > Are you referring to the configured MTU size or some other maximal size? > If MTU, then I don't seem to have this issue with the driver from > drivers/net/ethernet/mediatek/. > > > > Bj=C3=B8rn --=-=-= Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEEG8Yp69OQ2HB7X0l6Oeye3VZigbkFAlwPRMgACgkQOeye3VZi gbnDyQ/6A1mH6qdK6Ky02bWR/rhTEaDBEmambG/tDYmuNcldO9Ds3iCssFo2L7ER Um4ejU1mI3sWpymUsGKsGnaywmemrJ9AwCguTxKnCuHBgkjlcsAvy6fYyrDDrIZI lHIx1m3pgh8jZuE4Q4r7iZctvShkkJfyZo3aZHGxYxU1rxTnFGiaRW/kcryvvqT+ DEFJZvxGgX9VLGxYKArwvma8uJnIVAXamZheoAhl7sFXhtPfFnVP3HboXE52pEGT RQ7JEqdwp1g1/ZxDfNpOHMSDXmBrjb53gTqNECeeLNLCSqGjgem/YsEDLq02u/zA oJrbAB9V4rUQzv4Nzn7CDIUSMpcf3bYedy5gOQ8P5wPxJYsmr7Z13K9F8oNVZAgh YqjGpEBLn0QNK0kRNUetoBlAzTcfTIbVquoPiU495zPRDFPQPs4vNYrQ4O1qU+g4 qaDq+XevGNThFdjUjaf/iwdvfGOehbi+vi3an0gvoC6K/J23HdIe7xg6szRq+LUq 7X9ep6xB+0WWNUCreCkObHPmsnIQff9heh/tLW99CNqbCBF9CTR9r08tYddz6Kpd jdnW+Eb9ctLRbeCsHz4CGOxWmdu+HwtkO0537B9XMa6pZMt1Lw8Nqt58GXMI/Xvb I/PfDWMefRk9YnwT071imcUZsmRncZEXNyX+eIy3BZmhBXZ2Dj0= =sAzt -----END PGP SIGNATURE----- --=-=-=--