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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?bUjhsiYmLOYaMVpo8mBOJyqNJT/4hNLdFrrFT4ifi4YAVtMQ/jBj6vTIwuO1?= =?us-ascii?Q?mDJyB34Hl+5JBd7t15p5IpxH18JNyf2rIgKvIoU7r+Nadk5X/Lribsx6b/Vn?= =?us-ascii?Q?zKI5jwWK5Q8kbGBGXryZGRALi6uqI9jeUENyQSxsV5e/Y9LBfLd8UYuclBpE?= =?us-ascii?Q?j0PXTQjMNkbgKoIj/KCI3rgi3yrkrDvdF8UYngXEvEZQuJ6BPQOxgA3UOptz?= =?us-ascii?Q?BYuxMHKNIVSWXCvRE8GS1ZEb1QkCx79/06V1X8JzHcKTsYggkLk0alyraZfd?= =?us-ascii?Q?bAW7QG/2qw4BlMrRjlUUJD3fL4jtF1p/9fhoR2q3AakKzaz+ro0bqtpcGN3m?= =?us-ascii?Q?TS2jnhUMoNV+E+v6HCb2azvnxqUR5RsC4y0GHQTH2nP+M69WHcu/mc3Bw469?= =?us-ascii?Q?2Uf0J+6UwNScK9xm9kF3puCji/oRzo3+WTWAQKTGDbhcCX177dDk2YMaL9Iw?= =?us-ascii?Q?wOjkEiJDwWxIvHcMNXJByDwGwP02r4vjbQA/KKob3c41r87pxDIIUCTG5R7s?= =?us-ascii?Q?OIi1z1Zs+uM64ppXSnjRw0HHBwJiXnIHxlvHyzO9+BB+C2QFgjLujPjkJNbd?= =?us-ascii?Q?YKBwZQHIqKklE/8Fi5EpgbUovU79pnb64EW4DedsuWe/f71CX5hzjbPXUIOZ?= =?us-ascii?Q?QyGXn/i9UxMg+iWoJNRkdbOAGkOuzMWmDc2HJHzudufMasOgtfIcddxthIp1?= =?us-ascii?Q?qZFnmm/SISKP82Nz3m8cje9wrkxwlcjsaS6rDbFFHJaA9zgKR64iRq9qelP/?= =?us-ascii?Q?qYIgTTu/rLLCp5hXRtTIfOowHa1rvjM7Swi9IHs0IDdhppIy1MBA8Z0daB7w?= =?us-ascii?Q?HiSFl6ENFEHfc0WmXdnBANEt6aWaALPQmSpWZl5XpOgCQN582bJosaRSGkVQ?= =?us-ascii?Q?v+65PwKmOWQegv8gjTR+oiGXic7TOwMp+KVr0rBX7b2KW2JpE8NBMpZYFt/d?= =?us-ascii?Q?qkhVKiltlecnzX9pk3+JGnkocnpSHN20FksFquqHQzWFzv6MAdgpz1LNe0YH?= =?us-ascii?Q?6OptSdySPaBL+hr3R66Zi4tQWYUkx1oyHOaKTbazIPAut9VzpA3PlLFR8T1T?= =?us-ascii?Q?4LnHRqi+rhWGgi8blo7XE2zUSCIXE5odu8V2Atm1oCmU2jfPQ6Dcd/VKpMTp?= =?us-ascii?Q?yWqSSV+QC5Es6uDHfZ9fWU3WILYRoGKXn7QSdmjMeX1zRYON11udwntSCwSC?= =?us-ascii?Q?h8SZMJ4zPUPA87VrrckJUCLIV4siW+hDiEETkfYXQcOG7SPBnTGn8eauVEWF?= =?us-ascii?Q?TXnu/P341ki3rX//50Yx36fz1OpsZhEIT2cg9Owc0jkAwDyR98OwW7QJeq6Z?= =?us-ascii?Q?BBie0abVWIPEacFSZhbJp2F2i2/f5M/c4dMdF+CKUftwsZ9+3YxPFDp6dCk5?= =?us-ascii?Q?8z9fTkkbrseaq5Dz/68PqWDYIqoULWgDgAeRuPrxeWDy+2HUEultZP6vmaFk?= =?us-ascii?Q?m7yKU3zJON1BVUPJRPTqQo9M9R+xOcHoJTs7o5rfKBmhpaqRSmlKrLc4Y8y+?= =?us-ascii?Q?OT/utx41DPvTcs0ZkYNcgPIGG2FOfifTP60PRh4BSh++mXt7iYMkseB8rZVE?= =?us-ascii?Q?uxjTr1+U+KZEoq67L7p4VWY+OmJd45Pc5IFWsMMulKlhiHMos8YWXcjyOlXC?= =?us-ascii?Q?pA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5e8aff1c-dc1f-4268-db93-08dbeb899ba1 X-MS-Exchange-CrossTenant-AuthSource: BYAPR12MB2743.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Nov 2023 18:34:06.0270 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: fGPqNjcSDwVxE5VrJUlKdFfOO/cSYViipk0gBoyHzhDuWSFFApWRP0QHBc2uAA1rda5Xx6oJ8k1PCRuqUXlGhw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5058 On Wed, 15 Nov, 2023 10:10:53 -0500 Min Li wrote: > From: Min Li > > We used to assume 0x2010xxxx address. Now that > we need to access 0x2011xxxx address, we need > to support read/write the whole 32-bit address space. > > Signed-off-by: Min Li > --- > - Drop MAX_ABS_WRITE_PHASE_PICOSECONDS advised by Rahul > - Apply SCSR_ADDR to scrach register in idtcm_load_firmware advised by Simon > - Apply u32 to base in idtcm_output_enable advised by Simon > - Correct sync_ctrl0/1 parameter position for idtcm_write advised by Simon > > drivers/ptp/ptp_clockmatrix.c | 71 ++-- > drivers/ptp/ptp_clockmatrix.h | 32 +- > include/linux/mfd/idt8a340_reg.h | 542 ++++++++++++++++--------------- > 3 files changed, 331 insertions(+), 314 deletions(-) > > diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c > index f6f9d4adce04..1d5da77502e6 100644 > --- a/drivers/ptp/ptp_clockmatrix.c > +++ b/drivers/ptp/ptp_clockmatrix.c > @@ -1705,7 +1720,7 @@ static s32 idtcm_getmaxphase(struct ptp_clock_info *ptp __always_unused) > } > > /* > - * Internal function for implementing support for write phase offset > + * Maximum absolute value for write phase offset in picoseconds This documentation comment is wrong (this is meant for idtcm_getmaxphase). I think you might be generating patches without rebasing on the latest net-next tree? > * > * @channel: channel > * @delta_ns: delta in nanoseconds > @@ -1717,6 +1732,7 @@ static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns) > u8 i; > u8 buf[4] = {0}; > s32 phase_50ps; > + s64 offset_ps; > > if (channel->mode != PTP_PLL_MODE_WRITE_PHASE) { > err = channel->configure_write_phase(channel); > @@ -1724,7 +1740,8 @@ static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns) > return err; > } > > - phase_50ps = div_s64((s64)delta_ns * 1000, 50); > + offset_ps = (s64)delta_ns * 1000; > + phase_50ps = div_s64(offset_ps, 50); Sorry, I am not sure what this change has to do with 32-bit address space support. Seems like this was introduced due to not rebasing properly on top of latest changes? > > for (i = 0; i < 4; i++) { > buf[i] = phase_50ps & 0xff; -- Thanks, Rahul Rameshbabu