From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 194E0C352A1 for ; Wed, 7 Dec 2022 14:50:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230133AbiLGOuY (ORCPT ); Wed, 7 Dec 2022 09:50:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229709AbiLGOuS (ORCPT ); Wed, 7 Dec 2022 09:50:18 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCDED5802E for ; Wed, 7 Dec 2022 06:50:17 -0800 (PST) From: Kurt Kanzenbach DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1670424616; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=bo2/EVKSy2TU6OrVCoRaEt5X9l9631kaoSr2fn2PMCc=; b=NQQO4btqGkkCqNzZQaypTifSSD1EfLk6vSsnB2Mh8XBTFy7MZYhCiBV8kPZTIOTdK8uaFj QHlsB4GpvMLDQEpo5EzgfkFqqq3PAa/jVgDj3M9CR1d8+6SL9HDRLr6QHjKDtZRJVCdJrN No1ORBxiLcDHzQQhOMveE8owsOP8yhRyqEOjL4FOCbXn0qwnGpS6+rrNIyNscO/+M71+zT L2q8iNfprElJXNQrn7miM4Yhqb8gzzTXPvG8BlcRM1ynzsY3C/yvSpBokmYXFOTuCYs7TQ NJ6lfNezBLsX1HH7/y/3p8rOyJQnC0j39IznL+1V1V5zr2SEIPDcVm5gfF3QtA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1670424616; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=bo2/EVKSy2TU6OrVCoRaEt5X9l9631kaoSr2fn2PMCc=; b=O9gCK13SRcFAH/ixcPxGxTHo7aRvnoxYG/nf7kUp6ogu4b7jl2+XfFdHEkeqU1UcfSZ7QA P1CLeKbgti1o26AA== To: Andrew Lunn , Jakub Kicinski Cc: Piergiorgio Beruto , netdev@vger.kernel.org, peppe.cavallaro@st.com, Voon Weifeng , Rayagond Kokatanur , Jose Abreu , Antonio Borneo , Tan Tee Min Subject: Re: [PATCH net] stmmac: fix potential division by 0 In-Reply-To: References: <20221206182823.08e5f917@kernel.org> Date: Wed, 07 Dec 2022 15:50:13 +0100 Message-ID: <87v8mne09m.fsf@kurt> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha512; protocol="application/pgp-signature" Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org --=-=-= Content-Type: text/plain Content-Transfer-Encoding: quoted-printable On Wed Dec 07 2022, Andrew Lunn wrote: > On Tue, Dec 06, 2022 at 06:28:23PM -0800, Jakub Kicinski wrote: >> On Thu, 1 Dec 2022 15:49:37 +0100 Andrew Lunn wrote: >> > > The root cause is the MAC using the internal clock as a PTP reference >> > > (default), which should be allowed since the connection to an extern= al >> > > PTP clock is optional from an HW perspective. The internal clock see= ms >> > > to be derived from the MII clock speed, which is 2.5 MHz at 10 Mb/s.= =20=20 >> >=20 >> > I think we need help from somebody who understands PTP on this device. >> > The clock is clearly out of range, but how important is that to PTP? >> > Will PTP work if the value is clamped to 0xff? Or should we be >> > returning -EINVAL and disabling PTP because it has no chance of >> > working? >>=20 >> Indeed, we need some more info here :( Like does the PTP actually >> work with 2.5 MHz clock? The frequency adjustment only cares about=20 >> the addend, what is sub_second_inc thing? > > Hi Jakub > > I Cc: many of the people who worked on PTP with this hardware, and > nobody has replied. > > I think we should wait a couple more days, and then add a range check, > and disable PTP for invalid clocks. That might provoke feedback. Here's the Altera manual: https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/func= tional-description-of-the-emac.html Table 183 shows the minimum PTP frequencies and also states "Therefore, a higher PTP clock frequency gives better system performance.". So, I'd say using a clock of 2.5MHz seems possible, but will result in suboptimal precision. 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