On Thu Aug 20 2026, Jakub Kicinski wrote:
> On Wed, 19 Aug 2026 09:35:40 +0200 Kurt Kanzenbach wrote:
>> >> I want to use ETF Qdisc with hardware offload, which is currently not
>> >> possible on the stm32mp2.  
>> >
>> > Do you need multiple queues for ETF/normal traffic?
>> > Or one ETF and one "normal"?
>> >
>> > How do you sort the traffic between the queues?  
>> 
>> So the stm32mp2 has two CPU cores. I've isolated CPU1 for Profinet. That
>> one uses Tx/Rx queue 1 with ETF to reduce the Tx jitter. Everything else
>> is routed to Tx/Rx queue 0.
>> 
>> Config looks like this:
>> 
>> #
>> # Tx Assignment with SP.
>> #
>> # Tx Q 0 - Everything else
>> # Tx Q 1 - RTC
>> #
>> tc qdisc replace dev ${INTERFACE} handle 100 parent root mqprio num_tc 2 \
>>   map 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 \
>>   queues 1@0 1@1 \
>>   hw 1
>> 
>> #
>> # Enable Tx launch time support for TC 1.
>> #
>> tc qdisc replace dev ${INTERFACE} parent 100:2 etf \
>>   clockid CLOCK_TAI \
>>   delta 500000 \
>>   offload
>> 
>> On Rx incoming frames are steered via PCP field (vlan tagged).
>
> Thanks for explaining!

No problem.

>
>> >> It seems like a static configuration in the driver today. I basically
>> >> followed the same convention as dwmac-imx, dwmac-intel, dwmac-mediatek
>> >> and dwmac-qcom-ethqos. Only dwmac-socfpga does it differently.
>> >> 
>> >> Tx Launch Time requires a different DMA descriptor layout. Currently
>> >> tc_setup_etf() just returns -EINVAL if the DMA configuration is not
>> >> setup appropriately. I guess a dynamic configuration requires to change
>> >> the DMA config and perform a full release/open cycle.  
>> >
>> > release/open is not ideal but still better than hardcoding?  
>> 
>> For sure it's better than hardcoding :). But, again the driver does it
>> statically. Maybe there's a good reason for it. Maybe not. I'm not that
>> familiar with the stmmac driver. I'll prototype something to see whether
>> we can enable TBS at run time using the ETF Qdisc callback. It may take
>> some time though.
>
> I think the m in stmmac stand for 'mistake'. 

:D

> We need to start cleaning it up.

No objections here. I've briefly looked at the TBS thingy. I think we
just need to reconfigure one Tx queue instead of doing a full
release/open cycle. The XDP/ZC code does something similar. So the
infrastructure seems to be in place.

However, we need to keep track of what SoC implementation can enable TBS
on which queue. For gmac4 we can probably reuse tbs_en and for xgmac
there's is capability field tbs_ch_num. Let's see.

Thanks,
Kurt