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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown CC: , , , , References: <20240614130812.72425-1-christophe.roullier@foss.st.com> <20240614130812.72425-3-christophe.roullier@foss.st.com> <4c2f1bac-4957-4814-bf62-816340bd9ff6@denx.de> <09010b02-fb55-4c4b-9d0c-36bd0b370dc8@foss.st.com> <39d35f6d-4f82-43af-883b-a574b8a67a1a@denx.de> Content-Language: en-US From: Christophe ROULLIER In-Reply-To: <39d35f6d-4f82-43af-883b-a574b8a67a1a@denx.de> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-18_02,2024-06-17_01,2024-05-17_01 Hi Marek, On 6/17/24 17:57, Marek Vasut wrote: > On 6/17/24 1:23 PM, Christophe ROULLIER wrote: > > Hi, > >>>> +static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data >>>> *plat_dat) >>>> +{ >>>> +    struct stm32_dwmac *dwmac = plat_dat->bsp_priv; >>>> +    u32 reg = dwmac->mode_reg; >>>> +    int val = 0; >>>> + >>>> +    switch (plat_dat->mac_interface) { >>>> +    case PHY_INTERFACE_MODE_MII: >>>> +        break; >>> >>> dwmac->enable_eth_ck does not apply to MII mode ? Why ? >> >> It is like MP1 and MP13, nothing to set in syscfg register for case >> MII mode wo crystal. > > Have a look at STM32MP15xx RM0436 Figure 83. Peripheral clock > distribution for Ethernet. > > If RCC (top-left corner of the figure) generates 25 MHz MII clock > (yellow line) on eth_clk_fb (top-right corner), can I set > ETH_REF_CLK_SEL to position '1' and ETH_SEL[2] to '0' and feed ETH > (right side) clk_rx_i input with 25 MHz clock that way ? > > I seems like this should be possible, at least theoretically. Can you > check with the hardware/silicon people ? No it is not possible (it will work if speed (and frequency) is fixed  25Mhz=100Mbps, but for speed 10Mbps (2,5MHz) it will not work. (you can see than diviser are only for RMII mode) > > As a result, the MII/RMII mode would behave in a very similar way, and > so would GMII/RGMII mode behave in a very similar way. Effectively you > would end up with this (notice the fallthrough statements): > > +    case PHY_INTERFACE_MODE_RMII: > +        val = SYSCFG_ETHCR_ETH_SEL_RMII; > +        fallthrough; > +    case PHY_INTERFACE_MODE_MII: > +        if (dwmac->enable_eth_ck) > +            val |= SYSCFG_ETHCR_ETH_REF_CLK_SEL; > +        break; > + > +    case PHY_INTERFACE_MODE_RGMII: > +    case PHY_INTERFACE_MODE_RGMII_ID: > +    case PHY_INTERFACE_MODE_RGMII_RXID: > +    case PHY_INTERFACE_MODE_RGMII_TXID: > +        val = SYSCFG_ETHCR_ETH_SEL_RGMII; > +        fallthrough; > +    case PHY_INTERFACE_MODE_GMII: > +        if (dwmac->enable_eth_ck) > +            val |= SYSCFG_ETHCR_ETH_CLK_SEL; > +        break; > > [...]