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Sun, 18 Jun 2023 11:49:55 -0700 (PDT) Received: from [192.168.1.20] ([178.197.219.26]) by smtp.gmail.com with ESMTPSA id p13-20020a1709060e8d00b00982a99d9757sm4912284ejf.221.2023.06.18.11.49.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 18 Jun 2023 11:49:54 -0700 (PDT) Message-ID: <8d5f38e6-2ca6-2c61-da29-1d4d2a3df569@linaro.org> Date: Sun, 18 Jun 2023 20:49:52 +0200 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH 2/4] dt-bindings: clock: Add Intel Agilex5 clocks and resets Content-Language: en-US To: niravkumar.l.rabara@intel.com, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Dinh Nguyen , Michael Turquette , Stephen Boyd , Philipp Zabel , Wen Ping , Richard Cochran , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, Adrian Ng Ho Yin References: <20230618132235.728641-1-niravkumar.l.rabara@intel.com> <20230618132235.728641-3-niravkumar.l.rabara@intel.com> From: Krzysztof Kozlowski In-Reply-To: <20230618132235.728641-3-niravkumar.l.rabara@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net On 18/06/2023 15:22, niravkumar.l.rabara@intel.com wrote: > From: Niravkumar L Rabara > > Add clock and reset ID definitions for Intel Agilex5 SoCFPGA > > Co-developed-by: Teh Wen Ping > Signed-off-by: Teh Wen Ping > Signed-off-by: Niravkumar L Rabara > --- > .../bindings/clock/intel,agilex5.yaml | 42 ++++++++ > include/dt-bindings/clock/agilex5-clock.h | 100 ++++++++++++++++++ > .../dt-bindings/reset/altr,rst-mgr-agilex5.h | 79 ++++++++++++++ > 3 files changed, 221 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex5.yaml > create mode 100644 include/dt-bindings/clock/agilex5-clock.h > create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agilex5.h > > diff --git a/Documentation/devicetree/bindings/clock/intel,agilex5.yaml b/Documentation/devicetree/bindings/clock/intel,agilex5.yaml > new file mode 100644 > index 000000000000..e408c52deefa > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/intel,agilex5.yaml Filename matching compatible, so missing "clk" > @@ -0,0 +1,42 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/intel,agilex5.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Intel SoCFPGA Agilex5 platform clock controller binding Drop "binding" > + > +maintainers: > + - Teh Wen Ping > + - Niravkumar L Rabara > + > +description: > + The Intel Agilex5 Clock controller is an integrated clock controller, which > + generates and supplies to all modules. "generates and supplies" what? > + > +properties: > + compatible: > + const: intel,agilex5-clkmgr Why "clkmgr", not "clk"? You did not call it Clock manager anywhere in the description or title. > + > + '#clock-cells': > + const: 1 > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' Keep the same order as in properties: > + > +additionalProperties: false > + > +examples: > + # Clock controller node: > + - | > + clkmgr: clock-controller@10d10000 { > + compatible = "intel,agilex5-clkmgr"; > + reg = <0x10d10000 0x1000>; > + #clock-cells = <1>; > + }; > +... > diff --git a/include/dt-bindings/clock/agilex5-clock.h b/include/dt-bindings/clock/agilex5-clock.h > new file mode 100644 > index 000000000000..4505b352cd83 > --- /dev/null > +++ b/include/dt-bindings/clock/agilex5-clock.h Filename the same as binding. Missing vendor prefix, entirely different device name. > @@ -0,0 +1,100 @@ > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > +/* > + * Copyright (C) 2022, Intel Corporation > + */ ... > + > +#endif /* __AGILEX5_CLOCK_H */ > diff --git a/include/dt-bindings/reset/altr,rst-mgr-agilex5.h b/include/dt-bindings/reset/altr,rst-mgr-agilex5.h > new file mode 100644 > index 000000000000..81e5e8c89893 > --- /dev/null > +++ b/include/dt-bindings/reset/altr,rst-mgr-agilex5.h Same filename as binding. But why do you need this file? Your device is not a reset controller. Best regards, Krzysztof