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M." To: Romain Gantois , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: Maxime Chevallier , Thomas Petazzoni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, alvaro@linenoise.info Date: Fri, 13 Feb 2026 13:31:17 +0100 In-Reply-To: <20251110-sfp-1000basex-v2-0-dd5e8c1f5652@bootlin.com> References: <20251110-sfp-1000basex-v2-0-dd5e8c1f5652@bootlin.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-8 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Mon, 10 Nov 2025 10:24:52 +0100 Romain Gantois wrote: > Hi everyone, >=20 > This is version two of my series which adds support for using the > DP83869 PHY as a transceiver between an RGMII upper MAC and a > downstream 1000Base-X SFP module. Hi Romain, I am quite interested in this too, as we have a new version of a PCB in which we replaced a dp83848 (which only works with 100base-tx) with dp83869 with the intent of using 1000base-sx or similar SFPs. The are two different SFPs that I was able to use with dp83848 and would like to use them with the dp83869 as well: - RJ45 based: - Robofiber SFP-5000-RJ45A: 10/100Base-Tx SFP RJ45 - H!Fiber ASF-GE-T1 1000Base-T SFP RJ-25 Both of these already work with dp83869 with kernel 6.12, provided I set mode to DP83869_RGMII_100_BASE. If I try to make the 1000Base-T work at 1Gbps by setting op mode to DP83869_RGMII_1000_BASE it will still set speed to 100Mbps and will work just fine, but if I try to set speed to 1000, all data transfer stops. Personally, I could live with this, but I assume it should be possible for this SFP to work at 1Gbps. - Fiber based: - CISCO-FINISAR G155B3520KCD which I believe reports bit ETHTOOL_LINK_MODE_10000baseSR_Full_BIT - AVAGO AFBR-709SMZ which reports as 10gbase-r - ATGBICS AFBR-5710ALZ-C 1000BASE-SX The first two, even if they report as 10Gbase, did work with dp83848 at 100Mbps out of the box, but do not seem to work in any case with dp83869. The last one, 1000base-sx, is the one that I expected to work either out of the box or by using this set of patches of yours. However, none of them do work. What I did next, as the 10gbase was simply refused, was to apply the following patch above your series, which is more or less based on one of your previous patches from 2025. The key here is that I try hard to fallback to 100Mbps on every instance of non working SFP. So, I need that if linkmode_empty(sfp_support) because the 10/100 SFPs simply do not have any bit active to signal that capability, and I also set mode to RGMII_100_BASE in every case. So, with this patch: sfp amba_pl:sfp: module AVAGO AFBR-709SMZ rev G4.1 sn AA17053045F dc 170204 =20 TI DP83869 axienet-40c00000:01: dp83869_module_insert SFP compatible link m= ode: 10gbase-r TI DP83869 axienet-40c00000:01: incompatible PHY-to-SFP module link mode 10gbase-r! Try simply 10/100 Configuring network: xilinx_axienet 40c00000.ethernet eth0: PHY [axienet- 40c00000:01] driver [TI DP83869] (irq=3DPOLL) xilinx_axienet 40c00000.ethernet eth0: configuring for phy/1000base-x link = mode xilinx_axienet 40c00000.ethernet eth0: Link is Up - 100Mbps/Full - flow con= trol off And finally I have my other device answer to ping! So it seems that the DP83869, as is, won't be able to run at 1Gbps no matter what. >From the datasheet... wouldn't it be necessary to update OP_MODE_DECODE Register (Offset =3D 1DFh) [Reset =3D 0040h] CFG_OPMODE bits 2-0 to set val= ue 1 RGMII to 1000Base-X? diff --git c/dp83869.c w/dp83869.c index 31a2d4f..3857577 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -894,22 +895,63 @@ static void dp83869_module_remove(void *upstream) static int dp83869_module_insert(void *upstream, const struct sfp_eeprom_i= d *id) { struct phy_device *phydev =3D upstream; - const struct sfp_module_caps *caps; + __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support); + __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support); + DECLARE_PHY_INTERFACE_MASK(interfaces); struct dp83869_private *dp83869; + phy_interface_t interface; int ret; =20 - caps =3D sfp_get_module_caps(phydev->sfp_bus); + linkmode_zero(phy_support); + phylink_set(phy_support, 10000baseSR_Full); + phylink_set(phy_support, 1000baseT_Full); + phylink_set(phy_support, 1000baseX_Full); + phylink_set(phy_support, 100baseFX_Full); + phylink_set(phy_support, 100baseFX_Half); =20 - if (!linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, - caps->link_modes)) { - phydev_err(phydev, "incompatible SFP module inserted\n"); - return -EINVAL; + linkmode_zero(sfp_support); + sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces); + + sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces); + linkmode_and(sfp_support, phy_support, sfp_support); + + if (linkmode_empty(sfp_support)) { + phydev_err(phydev, "incompatible SFP module inserted, let's assume 10/100\n"); + + linkmode_zero(sfp_support); + sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces); + phylink_set(sfp_support, 100baseFX_Full); + linkmode_and(sfp_support, phy_support, sfp_support); + + if (linkmode_empty(sfp_support)) { + phydev_err(phydev, "incompatible SFP module inserted, 10/100 didn't work either\n"); + return -EINVAL; + } } =20 + interface =3D sfp_select_interface(phydev->sfp_bus, sfp_support); + phydev_info(phydev, "%s SFP compatible link mode: %s\n", __func__, + phy_modes(interface)); + dp83869 =3D phydev->priv; =20 - dp83869->mode =3D DP83869_RGMII_1000_BASE; - phydev->port =3D PORT_FIBRE; + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_100BASEX: + dp83869->mode =3D DP83869_RGMII_100_BASE; + phydev->port =3D PORT_FIBRE; + break; + case PHY_INTERFACE_MODE_1000BASEX: + dp83869->mode =3D DP83869_RGMII_1000_BASE; + phydev->port =3D PORT_FIBRE; + break; + default: + phydev_err(phydev, "incompatible PHY-to-SFP module link mode %s! Try simply 10/100\n", + phy_modes(interface)); + dp83869->mode =3D DP83869_RGMII_100_BASE; + phydev->port =3D PORT_FIBRE; + break; + } =20 ret =3D dp83869_configure_mode(phydev, dp83869); if (ret) It is absolutely possible that I misconfigured something, so here are the relevant parts of my DTS. Sadly, as you can see, we don't have GPIO access to the SFP pins, but at least they are properly pulled to the value that enables the SFP and the transmitter at all times. sfp0: sfp { compatible =3D "sff,sfp"; i2c-bus =3D <&axi_iic_0>; }; axi_ethernet_eth: ethernet@40c00000 { compatible =3D "xlnx,axi-ethernet-1.00.a"; reg =3D <0x40c00000 0x40000>; phy-handle =3D <&phy0>; interrupt-parent =3D <µblaze_0_axi_intc>; interrupts =3D <3>; xlnx,rxmem =3D <0x1000>; phy-mode =3D "1000base-x"; max-speed =3D <1000>; xlnx,txcsum =3D <0x2>; xlnx,rxcsum =3D <0x2>; clock-names =3D "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk"; clocks =3D <&clk_bus_0>, <&clk_bus_0>, <&clk_bus_0>, <&clk_bus_0>; axistream-connected =3D <&axi_ethernet_0_dma>; dma-names =3D "tx_chan0", "rx_chan0"; mdio { #address-cells =3D <1>; #size-cells =3D <0>; phy0: ethernet-phy@0 { sfp =3D <&sfp0>; reg =3D <1>; }; }; }; Thanks Best regards, --=20 Alvaro G. M.