[PATCH 0/5] PCI/MSI: Generalize no_64bit_msi into msi_addr_mask

[PATCH 0/5] PCI/MSI: Generalize no_64bit_msi into msi_addr_mask

[Vivian Wang]

The Sophgo SG2042 is a cursed machine in more ways than one.

The one way relevant to this patch series is that its PCIe controller
has neither INTx nor a low-address MSI doorbell wired up. Instead, the
only usable MSI doorbell is a SoC one at 0x7030010300, which is above
32-bit space.

Currently, the no_64bit_msi flag on a PCI device declares that a device
needs a 32-bit MSI address. Since no more precise indication is
possible, devices supporting less than 64 bits of MSI addresses are all
lumped into one "need 32-bit MSI address" bucket. This of course
prevents these devices from working with MSI enabled on SG2042 because a
32-bit MSI doorbell address is not possible. Combined with a lack of
INTx, some of them have trouble working on SG2042 at all.

There were previous dirtier attempts to allow overriding no_64bit_msi
for radeon [1] and hda/intel [2].

To fix this, generalize the single bit no_64bit_msi into a full address
mask msi_addr_mask to more precisely describe the restriction. The
existing DMA masks seems insufficient, as for e.g. radeon the
msi_addr_mask and coherent_dma_mask seems to be different on more recent
devices.

The patches are structured as follows:

- Patch 1 conservatively introduces msi_addr_mask, without introducing
  any functional changes (hopefully, if I've done everything right), by
  only using DMA_BIT_MASK(32) and DMA_BIT_MASK(64).
- The rest of the series actually make use of intermediate values of
  msi_addr_mask, and should be independently appliable. Patch 2 relaxes
  msi_verify_entries() to allow intermediate values of msi_addr_mask.
  Patch 3 onwards raises msi_addr_mask in individual device drivers.

Tested on SG2042 with a Radeon R5 220 which makes use of radeon and
hda/intel. PPC changes and pensanto/ionic changes are compile-tested
only, since I do not have the hardware.

I would appreciate if driver maintainers can take a look and see whether
the masks I've set makes sense, although I believe they shouldn't cause
problems on existing platforms. I'm also not familiar with PPC enough to
touch the arch/powerpc firmware calls further - help would be
appreciated.

My intention is that the first two patches are taken up by PCI
maintainers, and the rest go through the maintainers of individual
drivers since they could use more device-specific testing and review. If
this is not convenient I'll be happy to split it up or something.

[1]: https://lore.kernel.org/all/20251220163338.3852399-1-gaohan@iscas.ac.cn/
[2]: https://lore.kernel.org/all/20251220170501.3972438-1-gaohan@iscas.ac.cn/

---
Vivian Wang (5):
      PCI/MSI: Conservatively generalize no_64bit_msi into msi_addr_mask
      PCI/MSI: Check msi_addr_mask in msi_verify_entries()
      drm/radeon: Raise msi_addr_mask to 40 bits for pre-Bonaire
      ALSA: hda/intel: Raise msi_addr_mask to dma_bits
      [RFC net-next] net: ionic: Set msi_addr_mask to IONIC_ADDR_LEN-bit everywhere

 arch/powerpc/platforms/powernv/pci-ioda.c           |  2 +-
 arch/powerpc/platforms/pseries/msi.c                |  4 ++--
 drivers/gpu/drm/radeon/radeon_irq_kms.c             |  4 ++--
 drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c |  4 +---
 drivers/pci/msi/msi.c                               | 11 +++++++----
 drivers/pci/msi/pcidev_msi.c                        |  2 +-
 drivers/pci/probe.c                                 |  7 +++++++
 include/linux/pci.h                                 |  8 +++++++-
 sound/hda/controllers/intel.c                       | 10 +++++-----
 9 files changed, 33 insertions(+), 19 deletions(-)
---
base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8
change-id: 20251223-pci-msi-addr-mask-2d765a7eb390

Best regards,
-- 
Vivian "dramforever" Wang

[PATCH 1/5] PCI/MSI: Conservatively generalize no_64bit_msi into msi_addr_mask

[Vivian Wang]

Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
implement less than 64 address bits. This breaks on platforms where such
a device is assigned an MSI address higher than what's reachable.

Currently, we deal with this with a single no_64bit_msi flag, and
(notably on powerpc) use 32-bit MSI address for these devices. However,
on some platforms the MSI doorbell address is above 32-bit but within
device ability.

As a first step, conservatively generalize the single-bit flag
no_64bit_msi into msi_addr_mask. (The name msi_addr_mask is chosen to
avoid confusion with msi_mask.)

The translation is essentially:

- no_64bit_msi = 1    ->    msi_addr_mask = DMA_BIT_MASK(32)
- no_64bit_msi = 0    ->    msi_addr_mask = DMA_BIT_MASK(64)
- if (no_64bit_msi)   ->    if (msi_addr_mask < DMA_BIT_MASK(64))

Since no values other than DMA_BIT_MASK(32) and DMA_BIT_MASK(64) is
used, no functional change is intended. Future patches that make use of
intermediate values of msi_addr_mask will follow, allowing devices that
cannot use full 64-bit addresses for MSI to work on platforms with MSI
doorbell above 32-bit address space.

Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>

---

checkpatch complains about the comment include/linux/pci.h, which I have
formatted similarly with other comments in the vicinity.
---
 arch/powerpc/platforms/powernv/pci-ioda.c           | 2 +-
 arch/powerpc/platforms/pseries/msi.c                | 4 ++--
 drivers/gpu/drm/radeon/radeon_irq_kms.c             | 2 +-
 drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c | 2 +-
 drivers/pci/msi/msi.c                               | 2 +-
 drivers/pci/msi/pcidev_msi.c                        | 2 +-
 drivers/pci/probe.c                                 | 7 +++++++
 include/linux/pci.h                                 | 8 +++++++-
 sound/hda/controllers/intel.c                       | 2 +-
 9 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index b0c1d9d16fb5..1c78fdfb7b03 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1666,7 +1666,7 @@ static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
 		return -ENXIO;
 
 	/* Force 32-bit MSI on some broken devices */
-	if (dev->no_64bit_msi)
+	if (dev->msi_addr_mask < DMA_BIT_MASK(64))
 		is_64 = 0;
 
 	/* Assign XIVE to PE */
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c
index a82aaa786e9e..7473c7ca1db0 100644
--- a/arch/powerpc/platforms/pseries/msi.c
+++ b/arch/powerpc/platforms/pseries/msi.c
@@ -383,7 +383,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type,
 	 */
 again:
 	if (type == PCI_CAP_ID_MSI) {
-		if (pdev->no_64bit_msi) {
+		if (pdev->msi_addr_mask < DMA_BIT_MASK(64)) {
 			rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSI_FN, nvec);
 			if (rc < 0) {
 				/*
@@ -409,7 +409,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type,
 		if (use_32bit_msi_hack && rc > 0)
 			rtas_hack_32bit_msi_gen2(pdev);
 	} else {
-		if (pdev->no_64bit_msi)
+		if (pdev->msi_addr_mask < DMA_BIT_MASK(64))
 			rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSIX_FN, nvec);
 		else
 			rc = rtas_change_msi(pdn, RTAS_CHANGE_MSIX_FN, nvec);
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 9961251b44ba..d550554a6f3f 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -252,7 +252,7 @@ static bool radeon_msi_ok(struct radeon_device *rdev)
 	 */
 	if (rdev->family < CHIP_BONAIRE) {
 		dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n");
-		rdev->pdev->no_64bit_msi = 1;
+		rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32);
 	}
 
 	/* force MSI on */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
index 70d86c5f52fb..0671deae9a28 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
@@ -331,7 +331,7 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 
 #ifdef CONFIG_PPC64
 	/* Ensure MSI/MSI-X interrupts lie within addressable physical memory */
-	pdev->no_64bit_msi = 1;
+	pdev->msi_addr_mask = DMA_BIT_MASK(32);
 #endif
 
 	err = ionic_setup_one(ionic);
diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c
index 34d664139f48..48f5f03d1479 100644
--- a/drivers/pci/msi/msi.c
+++ b/drivers/pci/msi/msi.c
@@ -322,7 +322,7 @@ static int msi_verify_entries(struct pci_dev *dev)
 {
 	struct msi_desc *entry;
 
-	if (!dev->no_64bit_msi)
+	if (dev->msi_addr_mask == DMA_BIT_MASK(64))
 		return 0;
 
 	msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) {
diff --git a/drivers/pci/msi/pcidev_msi.c b/drivers/pci/msi/pcidev_msi.c
index 5520aff53b56..0b0346813092 100644
--- a/drivers/pci/msi/pcidev_msi.c
+++ b/drivers/pci/msi/pcidev_msi.c
@@ -24,7 +24,7 @@ void pci_msi_init(struct pci_dev *dev)
 	}
 
 	if (!(ctrl & PCI_MSI_FLAGS_64BIT))
-		dev->no_64bit_msi = 1;
+		dev->msi_addr_mask = DMA_BIT_MASK(32);
 }
 
 void pci_msix_init(struct pci_dev *dev)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 41183aed8f5d..a2bff57176a3 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2047,6 +2047,13 @@ int pci_setup_device(struct pci_dev *dev)
 	 */
 	dev->dma_mask = 0xffffffff;
 
+	/*
+	 * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit
+	 * if MSI (rather than MSI-X) capability does not have
+	 * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver.
+	 */
+	dev->msi_addr_mask = DMA_BIT_MASK(64);
+
 	dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
 		     dev->bus->number, PCI_SLOT(dev->devfn),
 		     PCI_FUNC(dev->devfn));
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 864775651c6f..0fe32fef0331 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -377,6 +377,13 @@ struct pci_dev {
 					   0xffffffff.  You only need to change
 					   this if your device has broken DMA
 					   or supports 64-bit transfers.  */
+	u64		msi_addr_mask;	/* Mask of the bits of bus address for
+					   MSI that this device implements.
+					   Normally set based on device
+					   capabilities. You only need to
+					   change this if your device claims
+					   to support 64-bit MSI but implements
+					   fewer than 64 address bits. */
 
 	struct device_dma_parameters dma_parms;
 
@@ -441,7 +448,6 @@ struct pci_dev {
 
 	unsigned int	is_busmaster:1;		/* Is busmaster */
 	unsigned int	no_msi:1;		/* May not use MSI */
-	unsigned int	no_64bit_msi:1;		/* May only use 32-bit MSIs */
 	unsigned int	block_cfg_access:1;	/* Config space access blocked */
 	unsigned int	broken_parity_status:1;	/* Generates false positive parity */
 	unsigned int	irq_reroute_variant:2;	/* Needs IRQ rerouting variant */
diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c
index 1e8e3d61291a..c9542ebdf7e2 100644
--- a/sound/hda/controllers/intel.c
+++ b/sound/hda/controllers/intel.c
@@ -1905,7 +1905,7 @@ static int azx_first_init(struct azx *chip)
 
 	if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) {
 		dev_dbg(card->dev, "Disabling 64bit MSI\n");
-		pci->no_64bit_msi = true;
+		pci->msi_addr_mask = DMA_BIT_MASK(32);
 	}
 
 	pci_set_master(pci);

-- 
2.51.2

[PATCH 2/5] PCI/MSI: Check msi_addr_mask in msi_verify_entries()

[Vivian Wang]

Instead of a 32-bit/64-bit dichotomy, check the MSI address against
msi_addr_mask.

This allows platforms with MSI doorbell above 32-bit address space to
work with devices without full 64-bit MSI address support, as long as
the doorbell is within addressable range of MSI of the device.

Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
---
 drivers/pci/msi/msi.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c
index 48f5f03d1479..2ecbcd6c436a 100644
--- a/drivers/pci/msi/msi.c
+++ b/drivers/pci/msi/msi.c
@@ -321,14 +321,17 @@ static int msi_setup_msi_desc(struct pci_dev *dev, int nvec,
 static int msi_verify_entries(struct pci_dev *dev)
 {
 	struct msi_desc *entry;
+	u64 address;
 
 	if (dev->msi_addr_mask == DMA_BIT_MASK(64))
 		return 0;
 
 	msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) {
-		if (entry->msg.address_hi) {
-			pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n",
-				entry->msg.address_hi, entry->msg.address_lo);
+		address = (u64)entry->msg.address_hi << 32 |
+			  entry->msg.address_lo;
+		if (address & ~dev->msi_addr_mask) {
+			pci_err(dev, "arch assigned 64-bit MSI address %llx above device MSI address mask %llx\n",
+				address, dev->msi_addr_mask);
 			break;
 		}
 	}

-- 
2.51.2

[PATCH 3/5] drm/radeon: Raise msi_addr_mask to 40 bits for pre-Bonaire

[Vivian Wang]

The code was originally written using no_64bit_msi, which restricts the
device to 32-bit MSI addresses.

Since msi_addr_mask is introduced, use DMA_BIT_MASK(40) instead of
DMA_BIT_MASK(32) here for msi_addr_mask, describing the restriction more
precisely and allowing these devices to work on platforms with MSI
doorbell address above 32-bit space, as long as it is within the
hardware restriction of 40-bit space.

Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
---
 drivers/gpu/drm/radeon/radeon_irq_kms.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index d550554a6f3f..ea519d43348b 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -251,8 +251,8 @@ static bool radeon_msi_ok(struct radeon_device *rdev)
 	 * IBM POWER servers, so we limit them
 	 */
 	if (rdev->family < CHIP_BONAIRE) {
-		dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n");
-		rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32);
+		dev_info(rdev->dev, "radeon: MSI limited to 40-bit\n");
+		rdev->pdev->msi_addr_mask = DMA_BIT_MASK(40);
 	}
 
 	/* force MSI on */

-- 
2.51.2

[PATCH 4/5] ALSA: hda/intel: Raise msi_addr_mask to dma_bits

[Vivian Wang]

The code was originally written using no_64bit_msi, which restricts the
device to 32-bit MSI addresses.

Since msi_addr_mask is introduced, use DMA_BIT_MASK(dma_bits) instead of
DMA_BIT_MASK(32) here for msi_addr_mask, describing the restriction more
precisely and allowing these devices to work on platforms with MSI
doorbell address above 32-bit space, as long as it is within the
hardware's addressable space.

Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>

---

hda/intel maintainers: I don't know if this is the correct restriction.
Please help with checking. Thanks.
---
 sound/hda/controllers/intel.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c
index c9542ebdf7e2..a44de2306a2b 100644
--- a/sound/hda/controllers/intel.c
+++ b/sound/hda/controllers/intel.c
@@ -1903,11 +1903,6 @@ static int azx_first_init(struct azx *chip)
 		chip->gts_present = true;
 #endif
 
-	if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) {
-		dev_dbg(card->dev, "Disabling 64bit MSI\n");
-		pci->msi_addr_mask = DMA_BIT_MASK(32);
-	}
-
 	pci_set_master(pci);
 
 	gcap = azx_readw(chip, GCAP);
@@ -1958,6 +1953,11 @@ static int azx_first_init(struct azx *chip)
 		dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
 	dma_set_max_seg_size(&pci->dev, UINT_MAX);
 
+	if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) {
+		dev_dbg(card->dev, "Restricting MSI to %u-bit\n", dma_bits);
+		pci->msi_addr_mask = DMA_BIT_MASK(dma_bits);
+	}
+
 	/* read number of streams from GCAP register instead of using
 	 * hardcoded value
 	 */

-- 
2.51.2

[PATCH RFC net-next 5/5] net: ionic: Set msi_addr_mask to IONIC_ADDR_LEN-bit everywhere

[Vivian Wang]

The code was originally written using no_64bit_msi, which restricts the
device to 32-bit MSI addresses.

Since msi_addr_mask is introduced, use DMA_BIT_MASK(IONIC_ADDR_LEN)
instead of DMA_BIT_MASK(32) here for msi_addr_mask, describing the
restriction more precisely and allowing these devices to work on
platforms with MSI doorbell address above 32-bit space, as long as it is
within the hardware's addressable space.

Also remove #ifdef CONFIG_PPC64 wrapped around it, since this is a
hardware restriction and not a platform one.

Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>

---

RFC because net-next is closed

pensando maintainers: I don't know if this is the actual restriction,
and do not have any Pensando device to test this. Please help with
checking this.  Thanks.
---
 drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
index 0671deae9a28..16133537c535 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
@@ -329,10 +329,8 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 		goto err_out;
 	}
 
-#ifdef CONFIG_PPC64
 	/* Ensure MSI/MSI-X interrupts lie within addressable physical memory */
-	pdev->msi_addr_mask = DMA_BIT_MASK(32);
-#endif
+	pdev->msi_addr_mask = DMA_BIT_MASK(IONIC_ADDR_LEN);
 
 	err = ionic_setup_one(ionic);
 	if (err)

-- 
2.51.2

Re: [PATCH 0/5] PCI/MSI: Generalize no_64bit_msi into msi_addr_mask

[Vivian Wang]

On 12/24/25 11:10, Vivian Wang wrote:
> The Sophgo SG2042 is a cursed machine in more ways than one.
>
[...]

> ---
> Vivian Wang (5):
>       PCI/MSI: Conservatively generalize no_64bit_msi into msi_addr_mask
>       PCI/MSI: Check msi_addr_mask in msi_verify_entries()
>       drm/radeon: Raise msi_addr_mask to 40 bits for pre-Bonaire
>       ALSA: hda/intel: Raise msi_addr_mask to dma_bits
>       [RFC net-next] net: ionic: Set msi_addr_mask to IONIC_ADDR_LEN-bit everywhere
>
>  arch/powerpc/platforms/powernv/pci-ioda.c           |  2 +-
>  arch/powerpc/platforms/pseries/msi.c                |  4 ++--
>  drivers/gpu/drm/radeon/radeon_irq_kms.c             |  4 ++--
>  drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c |  4 +---
>  drivers/pci/msi/msi.c                               | 11 +++++++----
>  drivers/pci/msi/pcidev_msi.c                        |  2 +-
>  drivers/pci/probe.c                                 |  7 +++++++
>  include/linux/pci.h                                 |  8 +++++++-
>  sound/hda/controllers/intel.c                       | 10 +++++-----
>  9 files changed, 33 insertions(+), 19 deletions(-)
> ---
> base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8
> change-id: 20251223-pci-msi-addr-mask-2d765a7eb390
>
> Best regards,

+cc linux-riscv and sophgo lists. Please see:

    https://lore.kernel.org/r/20251224-pci-msi-addr-mask-v1-0-05a6fcb4b4c0@iscas.ac.cn/

This is what happens when I rely on get_maintainers.pl too much...

Re: [PATCH 1/5] PCI/MSI: Conservatively generalize no_64bit_msi into msi_addr_mask

[Creeley, Brett]

On 12/23/2025 7:10 PM, Vivian Wang wrote:
> Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding.
>
>
> Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
> implement less than 64 address bits. This breaks on platforms where such
> a device is assigned an MSI address higher than what's reachable.
>
> Currently, we deal with this with a single no_64bit_msi flag, and
> (notably on powerpc) use 32-bit MSI address for these devices. However,
> on some platforms the MSI doorbell address is above 32-bit but within
> device ability.
>
> As a first step, conservatively generalize the single-bit flag
> no_64bit_msi into msi_addr_mask. (The name msi_addr_mask is chosen to
> avoid confusion with msi_mask.)
>
> The translation is essentially:
>
> - no_64bit_msi = 1    ->    msi_addr_mask = DMA_BIT_MASK(32)
> - no_64bit_msi = 0    ->    msi_addr_mask = DMA_BIT_MASK(64)
> - if (no_64bit_msi)   ->    if (msi_addr_mask < DMA_BIT_MASK(64))
>
> Since no values other than DMA_BIT_MASK(32) and DMA_BIT_MASK(64) is
> used, no functional change is intended. Future patches that make use of
> intermediate values of msi_addr_mask will follow, allowing devices that
> cannot use full 64-bit addresses for MSI to work on platforms with MSI
> doorbell above 32-bit address space.
>
> Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
>
> ---
>
> checkpatch complains about the comment include/linux/pci.h, which I have
> formatted similarly with other comments in the vicinity.
> ---
>   arch/powerpc/platforms/powernv/pci-ioda.c           | 2 +-
>   arch/powerpc/platforms/pseries/msi.c                | 4 ++--
>   drivers/gpu/drm/radeon/radeon_irq_kms.c             | 2 +-
>   drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c | 2 +-
>   drivers/pci/msi/msi.c                               | 2 +-
>   drivers/pci/msi/pcidev_msi.c                        | 2 +-
>   drivers/pci/probe.c                                 | 7 +++++++
>   include/linux/pci.h                                 | 8 +++++++-
>   sound/hda/controllers/intel.c                       | 2 +-
>   9 files changed, 22 insertions(+), 9 deletions(-)
>
> diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
> index b0c1d9d16fb5..1c78fdfb7b03 100644
> --- a/arch/powerpc/platforms/powernv/pci-ioda.c
> +++ b/arch/powerpc/platforms/powernv/pci-ioda.c
> @@ -1666,7 +1666,7 @@ static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
>                  return -ENXIO;
>
>          /* Force 32-bit MSI on some broken devices */
> -       if (dev->no_64bit_msi)
> +       if (dev->msi_addr_mask < DMA_BIT_MASK(64))
>                  is_64 = 0;
>
>          /* Assign XIVE to PE */
> diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c
> index a82aaa786e9e..7473c7ca1db0 100644
> --- a/arch/powerpc/platforms/pseries/msi.c
> +++ b/arch/powerpc/platforms/pseries/msi.c
> @@ -383,7 +383,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type,
>           */
>   again:
>          if (type == PCI_CAP_ID_MSI) {
> -               if (pdev->no_64bit_msi) {
> +               if (pdev->msi_addr_mask < DMA_BIT_MASK(64)) {
>                          rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSI_FN, nvec);
>                          if (rc < 0) {
>                                  /*
> @@ -409,7 +409,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type,
>                  if (use_32bit_msi_hack && rc > 0)
>                          rtas_hack_32bit_msi_gen2(pdev);
>          } else {
> -               if (pdev->no_64bit_msi)
> +               if (pdev->msi_addr_mask < DMA_BIT_MASK(64))
>                          rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSIX_FN, nvec);
>                  else
>                          rc = rtas_change_msi(pdn, RTAS_CHANGE_MSIX_FN, nvec);
> diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
> index 9961251b44ba..d550554a6f3f 100644
> --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
> +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
> @@ -252,7 +252,7 @@ static bool radeon_msi_ok(struct radeon_device *rdev)
>           */
>          if (rdev->family < CHIP_BONAIRE) {
>                  dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n");
> -               rdev->pdev->no_64bit_msi = 1;
> +               rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32);
>          }
>
>          /* force MSI on */
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
> index 70d86c5f52fb..0671deae9a28 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
> @@ -331,7 +331,7 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>
>   #ifdef CONFIG_PPC64
>          /* Ensure MSI/MSI-X interrupts lie within addressable physical memory */
> -       pdev->no_64bit_msi = 1;
> +       pdev->msi_addr_mask = DMA_BIT_MASK(32);

I know this is just an intermediate commit in the series, but does this 
retain the original intent?

Thanks,

Brett
>   #endif
>
>          err = ionic_setup_one(ionic);
> diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c
> index 34d664139f48..48f5f03d1479 100644
> --- a/drivers/pci/msi/msi.c
> +++ b/drivers/pci/msi/msi.c
> @@ -322,7 +322,7 @@ static int msi_verify_entries(struct pci_dev *dev)
>   {
>          struct msi_desc *entry;
>
> -       if (!dev->no_64bit_msi)
> +       if (dev->msi_addr_mask == DMA_BIT_MASK(64))
>                  return 0;
>
>          msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) {
> diff --git a/drivers/pci/msi/pcidev_msi.c b/drivers/pci/msi/pcidev_msi.c
> index 5520aff53b56..0b0346813092 100644
> --- a/drivers/pci/msi/pcidev_msi.c
> +++ b/drivers/pci/msi/pcidev_msi.c
> @@ -24,7 +24,7 @@ void pci_msi_init(struct pci_dev *dev)
>          }
>
>          if (!(ctrl & PCI_MSI_FLAGS_64BIT))
> -               dev->no_64bit_msi = 1;
> +               dev->msi_addr_mask = DMA_BIT_MASK(32);
>   }
>
>   void pci_msix_init(struct pci_dev *dev)
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 41183aed8f5d..a2bff57176a3 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -2047,6 +2047,13 @@ int pci_setup_device(struct pci_dev *dev)
>           */
>          dev->dma_mask = 0xffffffff;
>
> +       /*
> +        * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit
> +        * if MSI (rather than MSI-X) capability does not have
> +        * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver.
> +        */
> +       dev->msi_addr_mask = DMA_BIT_MASK(64);
> +
>          dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
>                       dev->bus->number, PCI_SLOT(dev->devfn),
>                       PCI_FUNC(dev->devfn));
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 864775651c6f..0fe32fef0331 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -377,6 +377,13 @@ struct pci_dev {
>                                             0xffffffff.  You only need to change
>                                             this if your device has broken DMA
>                                             or supports 64-bit transfers.  */
> +       u64             msi_addr_mask;  /* Mask of the bits of bus address for
> +                                          MSI that this device implements.
> +                                          Normally set based on device
> +                                          capabilities. You only need to
> +                                          change this if your device claims
> +                                          to support 64-bit MSI but implements
> +                                          fewer than 64 address bits. */
>
>          struct device_dma_parameters dma_parms;
>
> @@ -441,7 +448,6 @@ struct pci_dev {
>
>          unsigned int    is_busmaster:1;         /* Is busmaster */
>          unsigned int    no_msi:1;               /* May not use MSI */
> -       unsigned int    no_64bit_msi:1;         /* May only use 32-bit MSIs */
>          unsigned int    block_cfg_access:1;     /* Config space access blocked */
>          unsigned int    broken_parity_status:1; /* Generates false positive parity */
>          unsigned int    irq_reroute_variant:2;  /* Needs IRQ rerouting variant */
> diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c
> index 1e8e3d61291a..c9542ebdf7e2 100644
> --- a/sound/hda/controllers/intel.c
> +++ b/sound/hda/controllers/intel.c
> @@ -1905,7 +1905,7 @@ static int azx_first_init(struct azx *chip)
>
>          if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) {
>                  dev_dbg(card->dev, "Disabling 64bit MSI\n");
> -               pci->no_64bit_msi = true;
> +               pci->msi_addr_mask = DMA_BIT_MASK(32);
>          }
>
>          pci_set_master(pci);
>
> --
> 2.51.2
>

Re: [PATCH 1/5] PCI/MSI: Conservatively generalize no_64bit_msi into msi_addr_mask

[Vivian Wang]

On 1/6/26 02:05, Creeley, Brett wrote:
> On 12/23/2025 7:10 PM, Vivian Wang wrote:
>> Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding.
>>
>>
>> Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
>> implement less than 64 address bits. This breaks on platforms where such
>> a device is assigned an MSI address higher than what's reachable.
>>
>> Currently, we deal with this with a single no_64bit_msi flag, and
>> (notably on powerpc) use 32-bit MSI address for these devices. However,
>> on some platforms the MSI doorbell address is above 32-bit but within
>> device ability.
>>
>> As a first step, conservatively generalize the single-bit flag
>> no_64bit_msi into msi_addr_mask. (The name msi_addr_mask is chosen to
>> avoid confusion with msi_mask.)
>>
>> The translation is essentially:
>>
>> - no_64bit_msi = 1    ->    msi_addr_mask = DMA_BIT_MASK(32)
>> - no_64bit_msi = 0    ->    msi_addr_mask = DMA_BIT_MASK(64)
>> - if (no_64bit_msi)   ->    if (msi_addr_mask < DMA_BIT_MASK(64))
>>
>> Since no values other than DMA_BIT_MASK(32) and DMA_BIT_MASK(64) is
>> used, no functional change is intended. Future patches that make use of
>> intermediate values of msi_addr_mask will follow, allowing devices that
>> cannot use full 64-bit addresses for MSI to work on platforms with MSI
>> doorbell above 32-bit address space.
>>
>> Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
>>
>> ---
>>
>> checkpatch complains about the comment include/linux/pci.h, which I have
>> formatted similarly with other comments in the vicinity.
>> ---
>>   arch/powerpc/platforms/powernv/pci-ioda.c           | 2 +-
>>   arch/powerpc/platforms/pseries/msi.c                | 4 ++--
>>   drivers/gpu/drm/radeon/radeon_irq_kms.c             | 2 +-
>>   drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c | 2 +-
>>   drivers/pci/msi/msi.c                               | 2 +-
>>   drivers/pci/msi/pcidev_msi.c                        | 2 +-
>>   drivers/pci/probe.c                                 | 7 +++++++
>>   include/linux/pci.h                                 | 8 +++++++-
>>   sound/hda/controllers/intel.c                       | 2 +-
>>   9 files changed, 22 insertions(+), 9 deletions(-)
>>
>> diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
>> index b0c1d9d16fb5..1c78fdfb7b03 100644
>> --- a/arch/powerpc/platforms/powernv/pci-ioda.c
>> +++ b/arch/powerpc/platforms/powernv/pci-ioda.c
>> @@ -1666,7 +1666,7 @@ static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
>>                  return -ENXIO;
>>
>>          /* Force 32-bit MSI on some broken devices */
>> -       if (dev->no_64bit_msi)
>> +       if (dev->msi_addr_mask < DMA_BIT_MASK(64))
>>                  is_64 = 0;
>>
>>          /* Assign XIVE to PE */
>> diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c
>> index a82aaa786e9e..7473c7ca1db0 100644
>> --- a/arch/powerpc/platforms/pseries/msi.c
>> +++ b/arch/powerpc/platforms/pseries/msi.c
>> @@ -383,7 +383,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type,
>>           */
>>   again:
>>          if (type == PCI_CAP_ID_MSI) {
>> -               if (pdev->no_64bit_msi) {
>> +               if (pdev->msi_addr_mask < DMA_BIT_MASK(64)) {
>>                          rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSI_FN, nvec);
>>                          if (rc < 0) {
>>                                  /*
>> @@ -409,7 +409,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type,
>>                  if (use_32bit_msi_hack && rc > 0)
>>                          rtas_hack_32bit_msi_gen2(pdev);
>>          } else {
>> -               if (pdev->no_64bit_msi)
>> +               if (pdev->msi_addr_mask < DMA_BIT_MASK(64))
>>                          rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSIX_FN, nvec);
>>                  else
>>                          rc = rtas_change_msi(pdn, RTAS_CHANGE_MSIX_FN, nvec);
>> diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
>> index 9961251b44ba..d550554a6f3f 100644
>> --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
>> +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
>> @@ -252,7 +252,7 @@ static bool radeon_msi_ok(struct radeon_device *rdev)
>>           */
>>          if (rdev->family < CHIP_BONAIRE) {
>>                  dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n");
>> -               rdev->pdev->no_64bit_msi = 1;
>> +               rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32);
>>          }
>>
>>          /* force MSI on */
>> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
>> index 70d86c5f52fb..0671deae9a28 100644
>> --- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
>> +++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
>> @@ -331,7 +331,7 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>>
>>   #ifdef CONFIG_PPC64
>>          /* Ensure MSI/MSI-X interrupts lie within addressable physical memory */
>> -       pdev->no_64bit_msi = 1;
>> +       pdev->msi_addr_mask = DMA_BIT_MASK(32);
> I know this is just an intermediate commit in the series, but does this
> retain the original intent?
I do believe so, yes. The no_64bit_msi bit's meaning is the negation of
this bit found in the MSI capability:

    #define  PCI_MSI_FLAGS_64BIT    0x0080    /* 64-bit addresses allowed */

PCI_MSI_FLAGS_64BIT is set if this function handles PCI_MSI_ADDRESS_HI
and cleared if doesn't handle PCI_MSI_ADDRESS_HI. So with "no 64bit",
only PCI_MSI_ADDRESS_LO is usable, and MSI is limited to 32 bits. See
also old handling here:

>> diff --git a/drivers/pci/msi/pcidev_msi.c b/drivers/pci/msi/pcidev_msi.c
>> index 5520aff53b56..0b0346813092 100644
>> --- a/drivers/pci/msi/pcidev_msi.c
>> +++ b/drivers/pci/msi/pcidev_msi.c
>> @@ -24,7 +24,7 @@ void pci_msi_init(struct pci_dev *dev)
>>          }
>>
>>          if (!(ctrl & PCI_MSI_FLAGS_64BIT))
>> -               dev->no_64bit_msi = 1;
>> +               dev->msi_addr_mask = DMA_BIT_MASK(32);
>>   }
>>
>>   void pci_msix_init(struct pci_dev *dev)
... and the old definition of the flag here, where the comment
explicitly says no_64bit_msi means 32-bit:
>> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
>> index 41183aed8f5d..a2bff57176a3 100644
>> --- a/drivers/pci/probe.c
>> +++ b/drivers/pci/probe.c
>>
>> [...]
>>
>> @@ -441,7 +448,6 @@ struct pci_dev {
>>
>>          unsigned int    is_busmaster:1;         /* Is busmaster */
>>          unsigned int    no_msi:1;               /* May not use MSI */
>> -       unsigned int    no_64bit_msi:1;         /* May only use 32-bit MSIs */
>>          unsigned int    block_cfg_access:1;     /* Config space access blocked */
>>          unsigned int    broken_parity_status:1; /* Generates false positive parity */
>>          unsigned int    irq_reroute_variant:2;  /* Needs IRQ rerouting variant */
Vivian "dramforever" Wang

Re: [PATCH RFC net-next 5/5] net: ionic: Set msi_addr_mask to IONIC_ADDR_LEN-bit everywhere

[Creeley, Brett]

On 12/23/2025 7:10 PM, Vivian Wang wrote:
> Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding.
>
>
> The code was originally written using no_64bit_msi, which restricts the
> device to 32-bit MSI addresses.
>
> Since msi_addr_mask is introduced, use DMA_BIT_MASK(IONIC_ADDR_LEN)
> instead of DMA_BIT_MASK(32) here for msi_addr_mask, describing the
> restriction more precisely and allowing these devices to work on
> platforms with MSI doorbell address above 32-bit space, as long as it is
> within the hardware's addressable space.
>
> Also remove #ifdef CONFIG_PPC64 wrapped around it, since this is a
> hardware restriction and not a platform one.
>
> Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
>
> ---
>
> RFC because net-next is closed
>
> pensando maintainers: I don't know if this is the actual restriction,
> and do not have any Pensando device to test this. Please help with
> checking this.  Thanks.
> ---
>   drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c | 4 +---
>   1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
> index 0671deae9a28..16133537c535 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
> @@ -329,10 +329,8 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>                  goto err_out;
>          }
>
> -#ifdef CONFIG_PPC64
>          /* Ensure MSI/MSI-X interrupts lie within addressable physical memory */
> -       pdev->msi_addr_mask = DMA_BIT_MASK(32);
> -#endif
> +       pdev->msi_addr_mask = DMA_BIT_MASK(IONIC_ADDR_LEN);

I'm not sure that our device has MSI address limitations. I am getting 
an answer to this locally, but we might only be limited in the DMA 
address space.

I will get back on this as quickly as possible.

Thanks,

Brett
>
>          err = ionic_setup_one(ionic);
>          if (err)
>
> --
> 2.51.2
>

Re: [PATCH 0/5] PCI/MSI: Generalize no_64bit_msi into msi_addr_mask

[Christian König]

On 12/24/25 04:10, Vivian Wang wrote:
> The Sophgo SG2042 is a cursed machine in more ways than one.
> 
> The one way relevant to this patch series is that its PCIe controller
> has neither INTx nor a low-address MSI doorbell wired up. Instead, the
> only usable MSI doorbell is a SoC one at 0x7030010300, which is above
> 32-bit space.

Oh! That sounds like a really big show stopper for a lot of PCIe devices.

Pretty much all 32bit devices are impossible to work with that.

If I'm not completely mistaken that even makes the platform non-PCIe spec complaint.

> Currently, the no_64bit_msi flag on a PCI device declares that a device
> needs a 32-bit MSI address. Since no more precise indication is
> possible, devices supporting less than 64 bits of MSI addresses are all
> lumped into one "need 32-bit MSI address" bucket. This of course
> prevents these devices from working with MSI enabled on SG2042 because a
> 32-bit MSI doorbell address is not possible. Combined with a lack of
> INTx, some of them have trouble working on SG2042 at all.
> 
> There were previous dirtier attempts to allow overriding no_64bit_msi
> for radeon [1] and hda/intel [2].
> 
> To fix this, generalize the single bit no_64bit_msi into a full address
> mask msi_addr_mask to more precisely describe the restriction. The
> existing DMA masks seems insufficient, as for e.g. radeon the
> msi_addr_mask and coherent_dma_mask seems to be different on more recent
> devices.
> 
> The patches are structured as follows:
> 
> - Patch 1 conservatively introduces msi_addr_mask, without introducing
>   any functional changes (hopefully, if I've done everything right), by
>   only using DMA_BIT_MASK(32) and DMA_BIT_MASK(64).
> - The rest of the series actually make use of intermediate values of
>   msi_addr_mask, and should be independently appliable. Patch 2 relaxes
>   msi_verify_entries() to allow intermediate values of msi_addr_mask.
>   Patch 3 onwards raises msi_addr_mask in individual device drivers.
> 
> Tested on SG2042 with a Radeon R5 220 which makes use of radeon and
> hda/intel. PPC changes and pensanto/ionic changes are compile-tested
> only, since I do not have the hardware.
> 
> I would appreciate if driver maintainers can take a look and see whether
> the masks I've set makes sense, although I believe they shouldn't cause
> problems on existing platforms. I'm also not familiar with PPC enough to
> touch the arch/powerpc firmware calls further - help would be
> appreciated.

Over all the approach looks sane to me, but the radeon patch needs some changes.

Going to comment on the patch itself.

Regards,
Christian.

> 
> My intention is that the first two patches are taken up by PCI
> maintainers, and the rest go through the maintainers of individual
> drivers since they could use more device-specific testing and review. If
> this is not convenient I'll be happy to split it up or something.
> 
> [1]: https://lore.kernel.org/all/20251220163338.3852399-1-gaohan@iscas.ac.cn/
> [2]: https://lore.kernel.org/all/20251220170501.3972438-1-gaohan@iscas.ac.cn/
> 
> ---
> Vivian Wang (5):
>       PCI/MSI: Conservatively generalize no_64bit_msi into msi_addr_mask
>       PCI/MSI: Check msi_addr_mask in msi_verify_entries()
>       drm/radeon: Raise msi_addr_mask to 40 bits for pre-Bonaire
>       ALSA: hda/intel: Raise msi_addr_mask to dma_bits
>       [RFC net-next] net: ionic: Set msi_addr_mask to IONIC_ADDR_LEN-bit everywhere
> 
>  arch/powerpc/platforms/powernv/pci-ioda.c           |  2 +-
>  arch/powerpc/platforms/pseries/msi.c                |  4 ++--
>  drivers/gpu/drm/radeon/radeon_irq_kms.c             |  4 ++--
>  drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c |  4 +---
>  drivers/pci/msi/msi.c                               | 11 +++++++----
>  drivers/pci/msi/pcidev_msi.c                        |  2 +-
>  drivers/pci/probe.c                                 |  7 +++++++
>  include/linux/pci.h                                 |  8 +++++++-
>  sound/hda/controllers/intel.c                       | 10 +++++-----
>  9 files changed, 33 insertions(+), 19 deletions(-)
> ---
> base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8
> change-id: 20251223-pci-msi-addr-mask-2d765a7eb390
> 
> Best regards,

Re: [PATCH 3/5] drm/radeon: Raise msi_addr_mask to 40 bits for pre-Bonaire

[Christian König]

On 12/24/25 04:10, Vivian Wang wrote:
> The code was originally written using no_64bit_msi, which restricts the
> device to 32-bit MSI addresses.
> 
> Since msi_addr_mask is introduced, use DMA_BIT_MASK(40) instead of
> DMA_BIT_MASK(32) here for msi_addr_mask, describing the restriction more
> precisely and allowing these devices to work on platforms with MSI
> doorbell address above 32-bit space, as long as it is within the
> hardware restriction of 40-bit space.
> 
> Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
> ---
>  drivers/gpu/drm/radeon/radeon_irq_kms.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
> index d550554a6f3f..ea519d43348b 100644
> --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
> +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
> @@ -251,8 +251,8 @@ static bool radeon_msi_ok(struct radeon_device *rdev)
>  	 * IBM POWER servers, so we limit them
>  	 */
>  	if (rdev->family < CHIP_BONAIRE) {
> -		dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n");
> -		rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32);
> +		dev_info(rdev->dev, "radeon: MSI limited to 40-bit\n");
> +		rdev->pdev->msi_addr_mask = DMA_BIT_MASK(40);

Well, that is not even remotely correct.

Please move that close to the dma_set_mask_and_coherent() call in radeon_device_init() (file radeon_device.c).

The check there is most likely already what you need. Should be pretty straight forward.

Regards,
Christian.

>  	}
>  
>  	/* force MSI on */
> 

Re: [PATCH 3/5] drm/radeon: Raise msi_addr_mask to 40 bits for pre-Bonaire

[Vivian Wang]

On 1/7/26 23:20, Christian König wrote:
> On 12/24/25 04:10, Vivian Wang wrote:
>> The code was originally written using no_64bit_msi, which restricts the
>> device to 32-bit MSI addresses.
>>
>> Since msi_addr_mask is introduced, use DMA_BIT_MASK(40) instead of
>> DMA_BIT_MASK(32) here for msi_addr_mask, describing the restriction more
>> precisely and allowing these devices to work on platforms with MSI
>> doorbell address above 32-bit space, as long as it is within the
>> hardware restriction of 40-bit space.
>>
>> Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
>> ---
>>  drivers/gpu/drm/radeon/radeon_irq_kms.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
>> index d550554a6f3f..ea519d43348b 100644
>> --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
>> +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
>> @@ -251,8 +251,8 @@ static bool radeon_msi_ok(struct radeon_device *rdev)
>>  	 * IBM POWER servers, so we limit them
>>  	 */
>>  	if (rdev->family < CHIP_BONAIRE) {
>> -		dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n");
>> -		rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32);
>> +		dev_info(rdev->dev, "radeon: MSI limited to 40-bit\n");
>> +		rdev->pdev->msi_addr_mask = DMA_BIT_MASK(40);
> Well, that is not even remotely correct.
>
> Please move that close to the dma_set_mask_and_coherent() call in radeon_device_init() (file radeon_device.c).
>
> The check there is most likely already what you need. Should be pretty straight forward.

Thanks. In that case, maybe this msi_addr_mask thing was overcomplicated
after all. Maybe coherent_dma_mask is just the right thing to check anyway.

I'll see if I can figure something out. Of course I need to keep the
logic for Power still working...

Vivian "dramforever" Wang