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Mon, 30 Jun 2025 09:36:10 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: T1801f58283c6cf22 Date: Mon, 30 Jun 2025 14:35:50 +0100 From: "Jiaxun Yang" To: =?UTF-8?Q?Th=C3=A9o_Lebrun?= , "Andrew Lunn" , "David S . Miller" , "Eric Dumazet" , "Jakub Kicinski" , "Paolo Abeni" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Nicolas Ferre" , "Claudiu Beznea" , "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Alexandre Ghiti" , "Samuel Holland" , "Richard Cochran" , "Russell King" , "Thomas Bogendoerfer" , "Vladimir Kondratiev" , "Gregory CLEMENT" , "Cyrille Pitchen" , "Harini Katakam" , "Rafal Ozieblo" , "Haavard Skinnemoen" , "Jeff Garzik" Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, "linux-mips@vger.kernel.org" , "Thomas Petazzoni" , "Tawfik Bayouk" Message-Id: <984c1bea-7020-4121-9fea-7d657a5e8da1@app.fastmail.com> In-Reply-To: <20250627-macb-v2-16-ff8207d0bb77@bootlin.com> References: <20250627-macb-v2-0-ff8207d0bb77@bootlin.com> <20250627-macb-v2-16-ff8207d0bb77@bootlin.com> Subject: Re: [PATCH net-next v2 16/18] MIPS: mobileye: add EyeQ5 DMA IOCU support Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82025=E5=B9=B46=E6=9C=8827=E6=97=A5=E5=91=A8=E4=BA=94 =E4=B8=8A=E5= =8D=8810:09=EF=BC=8CTh=C3=A9o Lebrun=E5=86=99=E9=81=93=EF=BC=9A > Both Cadence GEM Ethernet controllers on EyeQ5 are hardwired through C= M3 > IO Coherency Units (IOCU). For DMA coherent accesses, BIT(36) must be > set in DMA addresses. Hi Th=C3=A9o, Just quick question, it seems like this special driver is only applying a fixed offset (1 << 36) to the DMA physical address, can we achieve that = with dma-ranges property in DeviceTree? I belive: ``` dma-coherent; # Bus addr # Phys # Size dma-ranges =3D <0x10 0x00000000 0x0 0x0 0x10 0>; ``` Will do the job. Thanks Jiaxun > > Implement that in platform-specific dma_map_ops which get attached to > both instances of `cdns,eyeq5-gem` through a notifier block. > > Signed-off-by: Th=C3=A9o Lebrun > --- > MAINTAINERS | 2 +- > arch/mips/mobileye/Kconfig | 1 + > arch/mips/mobileye/Makefile | 2 + > arch/mips/mobileye/eyeq5-iocu-dma.c | 160 +++++++++++++++++++++++++++= +++++++++ > 4 files changed, 164 insertions(+), 1 deletion(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index=20 > bb9df569a3fff41ab40d7da5843f1e8564b47bf2..7ee68d7f8e8d0632846f59579412= 458e301bd8fb=20 > 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -16789,7 +16789,7 @@=20 > F: Documentation/devicetree/bindings/mips/mobileye.yaml > F: Documentation/devicetree/bindings/soc/mobileye/ > F: arch/mips/boot/dts/mobileye/ > F: arch/mips/configs/eyeq5_defconfig > -F: arch/mips/mobileye/board-epm5.its.S > +F: arch/mips/mobileye/ > F: drivers/clk/clk-eyeq.c > F: drivers/pinctrl/pinctrl-eyeq5.c > F: drivers/reset/reset-eyeq.c > diff --git a/arch/mips/mobileye/Kconfig b/arch/mips/mobileye/Kconfig > index=20 > f9abb2d6e1787dbc5a173db48606ed5a02088e41..b9040f3a9b3ddc7f5addcd8e5f11= 0cb9c775b6b1=20 > 100644 > --- a/arch/mips/mobileye/Kconfig > +++ b/arch/mips/mobileye/Kconfig > @@ -9,6 +9,7 @@ choice >=20 > config MACH_EYEQ5 > bool "Mobileye EyeQ5 SoC" > + select ARCH_HAS_DMA_OPS >=20 > config MACH_EYEQ6H > bool "Mobileye EyeQ6H SoC" > diff --git a/arch/mips/mobileye/Makefile b/arch/mips/mobileye/Makefile > index=20 > 315c06b689cfbb83f9f205d1140ecf5058e2aa02..50fc7d0ae167c3fb3dc8585bcd45= 583c6cc3f2d2=20 > 100644 > --- a/arch/mips/mobileye/Makefile > +++ b/arch/mips/mobileye/Makefile > @@ -1 +1,3 @@ > # SPDX-License-Identifier: GPL-2.0-or-later > + > +obj-$(CONFIG_MACH_EYEQ5) +=3D eyeq5-iocu-dma.o > diff --git a/arch/mips/mobileye/eyeq5-iocu-dma.c=20 > b/arch/mips/mobileye/eyeq5-iocu-dma.c > new file mode 100644 > index=20 > 0000000000000000000000000000000000000000..71d1c35f911636db141c4467dccc= 405af69835ec > --- /dev/null > +++ b/arch/mips/mobileye/eyeq5-iocu-dma.c > @@ -0,0 +1,160 @@ > +// SPDX-License-Identifier: GPL-2.0 > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +static void *eyeq5_iocu_alloc(struct device *dev, size_t size, > + dma_addr_t *dma_handle, gfp_t gfp, > + unsigned long attrs) > +{ > + void *p =3D dma_direct_alloc(dev, size, dma_handle, gfp, attrs); > + > + *dma_handle |=3D BIT_ULL(36); > + return p; > +} > + > +static void eyeq5_iocu_free(struct device *dev, size_t size, > + void *vaddr, dma_addr_t dma_handle, > + unsigned long attrs) > +{ > + dma_handle &=3D ~BIT_ULL(36); > + dma_direct_free(dev, size, vaddr, dma_handle, attrs); > +} > + > +static int eyeq5_iocu_mmap(struct device *dev, struct vm_area_struct=20 > *vma, > + void *cpu_addr, dma_addr_t dma_addr, size_t size, > + unsigned long attrs) > +{ > + unsigned long pfn =3D PHYS_PFN(dma_to_phys(dev, dma_addr)); > + unsigned long count =3D PAGE_ALIGN(size) >> PAGE_SHIFT; > + unsigned long user_count =3D vma_pages(vma); > + int ret; > + > + vma->vm_page_prot =3D dma_pgprot(dev, vma->vm_page_prot, attrs); > + > + if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret)) > + return ret; > + > + if (vma->vm_pgoff >=3D count || user_count > count - vma->vm_pgoff) > + return -ENXIO; > + > + return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff, > + user_count << PAGE_SHIFT, vma->vm_page_prot); > +} > + > +static int eyeq5_iocu_get_sgtable(struct device *dev, struct sg_table=20 > *sgt, > + void *cpu_addr, dma_addr_t dma_addr, size_t size, > + unsigned long attrs) > +{ > + struct page *page =3D virt_to_page(cpu_addr); > + int ret; > + > + ret =3D sg_alloc_table(sgt, 1, GFP_KERNEL); > + if (!ret) > + sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); > + return ret; > +} > + > +static dma_addr_t eyeq5_iocu_map_page(struct device *dev, struct page=20 > *page, > + unsigned long offset, size_t size, > + enum dma_data_direction dir, > + unsigned long attrs) > +{ > + phys_addr_t phys =3D page_to_phys(page) + offset; > + > + /* BIT(36) toggles routing through IOCU for DMA operations. */ > + return phys_to_dma(dev, phys) | BIT_ULL(36); > +} > + > +static void eyeq5_iocu_unmap_page(struct device *dev, dma_addr_t=20 > dma_handle, > + size_t size, enum dma_data_direction dir, > + unsigned long attrs) > +{ > +} > + > +static int eyeq5_iocu_map_sg(struct device *dev, struct scatterlist=20 > *sgl, > + int nents, enum dma_data_direction dir, > + unsigned long attrs) > +{ > + struct scatterlist *sg; > + int i; > + > + for_each_sg(sgl, sg, nents, i) { > + sg->dma_address =3D eyeq5_iocu_map_page(dev, sg_page(sg), > + sg->offset, sg->length, > + dir, attrs); > + if (sg->dma_address =3D=3D DMA_MAPPING_ERROR) > + return 0; /* No cleanup because ->unmap_page() is a no-op. */ > + sg_dma_len(sg) =3D sg->length; > + } > + > + return nents; > +} > + > +static void eyeq5_iocu_unmap_sg(struct device *dev, struct scatterlis= t=20 > *sgl, > + int nents, enum dma_data_direction dir, > + unsigned long attrs) > +{ > + /* We know page ->unmap_page() is a no-op. */ > +} > + > +const struct dma_map_ops eyeq5_iocu_ops =3D { > + .alloc =3D eyeq5_iocu_alloc, > + .free =3D eyeq5_iocu_free, > + .alloc_pages_op =3D dma_direct_alloc_pages, > + .free_pages =3D dma_direct_free_pages, > + .mmap =3D eyeq5_iocu_mmap, > + .get_sgtable =3D eyeq5_iocu_get_sgtable, > + .map_page =3D eyeq5_iocu_map_page, > + .unmap_page =3D eyeq5_iocu_unmap_page, > + .map_sg =3D eyeq5_iocu_map_sg, > + .unmap_sg =3D eyeq5_iocu_unmap_sg, > + .get_required_mask =3D dma_direct_get_required_mask, > +}; > +EXPORT_SYMBOL(eyeq5_iocu_ops); > + > +static int eyeq5_iocu_notifier(struct notifier_block *nb, > + unsigned long event, > + void *data) > +{ > + struct device *dev =3D data; > + > + /* > + * IOCU routing is hardwired; we must use our above custom > + * routines for cache-coherent DMA on ethernet interfaces. > + */ > + if (event =3D=3D BUS_NOTIFY_ADD_DEVICE && > + device_is_compatible(dev, "mobileye,eyeq5-gem")) { > + set_dma_ops(dev, &eyeq5_iocu_ops); > + return NOTIFY_OK; > + } > + > + return NOTIFY_DONE; > +} > + > +static struct notifier_block eyeq5_iocu_nb =3D { > + .notifier_call =3D eyeq5_iocu_notifier, > +}; > + > +static int __init eyeq5_iocu_init(void) > +{ > + return bus_register_notifier(&platform_bus_type, &eyeq5_iocu_nb); > +} > +postcore_initcall(eyeq5_iocu_init); > > --=20 > 2.50.0 --=20 - Jiaxun