From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26F1DC76196 for ; Tue, 28 Mar 2023 12:30:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230258AbjC1Mat (ORCPT ); Tue, 28 Mar 2023 08:30:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229436AbjC1Mat (ORCPT ); Tue, 28 Mar 2023 08:30:49 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6EA186BE; Tue, 28 Mar 2023 05:30:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=p1vueGhlFqaDJRo3Ow4NaqQoeuYHMXia7i1M7wo4oX0=; b=IWf53GWYdLA9Up9WtqneknvJxX ztNLrBxlFPW0QeMFs36BDZewTV3YGh98GPqTbyplhKj3H7gS9BFnkTn44mJAlJBWfZNCpWXDkZ/IZ 5eyAwBA1jNo3833RCoi+FCliKJ/9copbULIfNCKPGbjJEQBopCeYwlMn+yO+TXpkAt6g=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1ph8TF-008dwt-UM; Tue, 28 Mar 2023 14:30:37 +0200 Date: Tue, 28 Mar 2023 14:30:37 +0200 From: Andrew Lunn To: Marek =?iso-8859-1?Q?Beh=FAn?= Cc: Gustav Ekelund , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , kernel@axis.com, Gustav Ekelund , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net] net: dsa: mv88e6xxx: Reset mv88e6393x watchdog register Message-ID: <9ba1722a-8dd7-4d6d-bade-b4c702c8387f@lunn.ch> References: <20230328115511.400145-1-gustav.ekelund@axis.com> <20230328120604.zawfeskqs4yhlze6@kandell> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230328120604.zawfeskqs4yhlze6@kandell> Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org > > +static int mv88e6393x_watchdog_action(struct mv88e6xxx_chip *chip, int irq) > > +{ > > + mv88e6390_watchdog_action(chip, irq); > > + > > + mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL, > > + MV88E6390_G2_WDOG_CTL_UPDATE | > > + MV88E6390_G2_WDOG_CTL_PTR_EVENT); > > + > > + return IRQ_HANDLED; > > +} > > Shouldn't this update be in .irq_setup() method? In the commit message > you're saying that the problem is that bits aren't cleared with SW > reset. So I would guess that the change should be in the setup of > watchdog IRQ, not in IRQ action? I think it is a bit more complex than that. At least for the 6352, which i just looked at the data sheet, the interrupt bits are listed as "ROC". Which is missing from the list of definitions, but seems to mean Read Only, Clear on read. So even if it was not cleared on software reset, it would only fire once, and then be cleared. The problem description here is that it does not clear on read, it needs an explicit write. Which suggests Marvell changed it for the 6393. So i have a couple of questions: 1) Is this new behaviour limited to the 6393, or does the 6390 also need this write? 2) What about other interrupts? Is this the only one which has changed behaviour? Andrew