Re: [PATCH net-next v3 1/4] net: rnpgbe: Add interrupt handling

[Yibo Dong <dong100@mucse.com>]

On Thu, May 07, 2026 at 01:30:55PM +0100, Vadim Fedorenko wrote:
> On 07/05/2026 09:15, Dong Yibo wrote:
> > Add comprehensive interrupt handling for the RNPGBE driver:
> > - Implement msi-x/msi interrupt configuration and management
> > - Create library functions for interrupt registration and cleanup
> > 
> > This infrastructure enables proper interrupt handling for the
> > RNPGBE driver.
> > 
> 
> [...]
> 
> > +/**
> > + * rnpgbe_set_interrupt_capability - Set MSI-X or MSI if supported
> > + * @mucse: pointer to private structure
> > + *
> > + * Attempt to configure the interrupts using the best available
> > + * capabilities of the hardware.
> > + *
> > + * @return: 0 on success, negative on failure
> > + **/
> > +static int rnpgbe_set_interrupt_capability(struct mucse *mucse)
> > +{
> > +	int v_budget;
> > +
> > +	v_budget = min_t(int, mucse->num_tx_queues, mucse->num_rx_queues);
> > +	v_budget = min_t(int, v_budget, MAX_Q_VECTORS);
> 
> these 2 lines can be simplified to
> 
> min3(mucse->num_tx_queues, mucse->num_rx_queues, MAX_Q_VECTORS);
> 

Got it, I will update this.

> > +	v_budget = min_t(int, v_budget, num_online_cpus());
> > +	/* add one vector for mbx */> +	v_budget += 1;
> > +	v_budget = pci_alloc_irq_vectors(mucse->pdev, 1, v_budget,
> > +					 PCI_IRQ_MSI | PCI_IRQ_MSIX);
> > +	if (v_budget < 0)
> > +		return v_budget;
> > +
> > +	if (mucse->pdev->msix_enabled) {
> > +		/* q_vector not include mbx */
> > +		if (v_budget > 1) {
> > +			mucse->flags |= M_FLAG_MSIX_EN;
> > +			mucse->num_q_vectors = v_budget - 1;
> > +		} else {
> > +			mucse->flags |= M_FLAG_MSIX_SINGLE_EN;
> > +			mucse->num_q_vectors = 1;
> > +		}
> > +	} else {
> > +		/* msi use only 1 irq */
> > +		mucse->num_q_vectors = 1;
> > +		mucse->flags |= M_FLAG_MSI_EN;
> > +	}
> 
> How will it work in case it's only 1 vector allocated? AFAIU, you need at
> least 2 irq vectors - 1 for queue processing, another one for mbx.
> 

Mbx and tx/rx irq share 1 irq. And in fact, Hw only support 1 msi irq.
Just like ixgbe_intr in intel drivers.

> > +
> > +	return 0;
> > +}
> 

Thanks for your feedback.