Re: drivers/net/enic/vnic_cq.c

[Scott Feldman <sfeldma@nuovasystems.com>]

On 10/10/08 11:58 AM, "David Miller" <davem@davemloft.net> wrote:

> From: Scott Feldman <sfeldma@nuovasystems.com>
> Date: Fri, 10 Oct 2008 11:29:23 -0700
>> Yes, enic hw provides atomic read/write for 64-bit regs even if register is
>> accessed with 32-bit read/writes.
> 
> Sure, and this is why 32-bit arch's don't provide readq/writeq
> implementations,
> things are much more subtle here.
> 
> The hardware may allow 2 32-bit writes to a 64-bit register, but...
> 
> Are there potential problems when the register is half-way updated?
> 
> For example, consider a ring index where the upper and lower 32-bits
> are actually significant.  If you change the top part and then the
> bottom part, in the intermediate step there is an invalid state and
> the card might try to access an invalid ring index.

Yes, I'd like to retract my original remark.  :(  There is a mechanism for
atomic access to a wide register, but it's not enabled for the register
cases in question, and even if it was, an intermediate access to another
address would invalidate the mechanism, as you point out.  So...
 
> Then also, of course, the driver itself has to make sure it does
> enough locking to make sure a partial 64-bit update isn't interrupted
> by a parallel one on another cpu to the same register but I'll assume
> the driver takes care of that here :-)

...There is enough locking.

-scott