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Wed, 03 Sep 2025 02:55:45 -0700 (PDT) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250901224327.3429099-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250901224327.3429099-2-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250902-enlightened-hidden-copperhead-4eefdf@kuoka> In-Reply-To: From: "Lad, Prabhakar" Date: Wed, 3 Sep 2025 10:55:19 +0100 X-Gm-Features: Ac12FXxib3LE_thJdEpo4IuHLom6nbssJ6zefKky-qUN2oXf5_wvK5du5lizrRo Message-ID: Subject: Re: [PATCH net-next 01/10] dt-bindings: net: pcs: renesas,rzn1-miic: Document RZ/T2H and RZ/N2H SoCs To: Geert Uytterhoeven Cc: Krzysztof Kozlowski , =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Wolfram Sang , linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Geert, Thank you for the review. On Wed, Sep 3, 2025 at 10:12=E2=80=AFAM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > Thanks for your patch! > > On Tue, 2 Sept 2025 at 14:17, Lad, Prabhakar = wrote: > > On Tue, Sep 2, 2025 at 9:45=E2=80=AFAM Krzysztof Kozlowski wrote: > > > On Mon, Sep 01, 2025 at 11:43:14PM +0100, Prabhakar wrote: > > > > From: Lad Prabhakar > > > > > > > > Extend the RZN1 MIIC device-tree binding schema to cover the RZ/T2H > > > > and RZ/N2H SoCs. These SoCs have a MIIC converter similar to RZ/N1,= but > > > > with some differences: > > > > > > > > - RZ/T2H has two reset lines; RZ/N1 has none. > > > > - RZ/N1 supports 5 MIIC ports, whereas RZ/T2H supports 4 ports. > > > > - On RZ/N1, MIIC ports can be mapped to various endpoints such as R= TOS > > > > MAC ports, switch ports, EtherCAT ports, SERCOS ports, HSR ports,= or > > > > fixed PHY ports (covering PHY input indices 0-13). On RZ/T2H, por= ts > > > > can connect to EtherCAT slave ports, Ethernet switch ports, or GM= AC > > > > ports (mapped to PHY input indices 0-8). > > > > - There are register bit differences between the SoCs, and RZ/N1 ha= s > > > > additional registers currently unused by the driver. > > > > - On RZ/T2H, the switch is connected to GMAC0 whereas on RZ/N1 the > > > > switch can be connected to GMAC2/HW-RTOS GMAC. > > > > > > > > To accommodate these differences, a new generic compatible string > > > > `renesas,rzt2h-miic` is introduced for both RZ/T2H and RZ/N2H varia= nts. > > Until now, we didn't have any family-specific "renesas,rzt2h-*" > compatible values. Instead, we always used " renesas,r9a09g077-" > as a fallback for "renesas,r9a09g087-". > Is there any good reason to start deviating from this? > Right good point, I'll continue using the previous approach and use T2H compatible as a fallback for N2H. > > > > > > > > The DT schema is updated to validate these differences and ensure p= roper > > > > port and reset configurations per SoC. > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > --- a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.y= aml > > > > +++ b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.y= aml > > > > @@ -4,13 +4,14 @@ > > > > $id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml# > > > > $schema: http://devicetree.org/meta-schemas/core.yaml# > > > > > > > > -title: Renesas RZ/N1 MII converter > > > > +title: Renesas RZ/{N1, N2H, T2H} MII converter > > > > > > Don't use regex here. RZ/N1, RZ/N2H and TZ/T2H.... > > > > > Ok, I will use it as above (s/TZ/T2H/RZ/T2H). > > s@TZ/T2H@RZ/T2H@ ;-) > :-) Cheers, Prabhakar