* [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support
@ 2025-06-26 8:09 Paul Kocialkowski
2025-06-26 8:09 ` [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name Paul Kocialkowski
` (6 more replies)
0 siblings, 7 replies; 30+ messages in thread
From: Paul Kocialkowski @ 2025-06-26 8:09 UTC (permalink / raw)
To: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio
Cc: Andrew Lunn, David S . Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Linus Walleij,
Andre Przywara, Paul Kocialkowski
This series adds support for the Alwinner A100/A133 Ethernet MAC (EMAC)
and uses it in the Liontron H-A133L board.
Paul Kocialkowski (5):
pinctrl: sunxi: Fix a100 emac pin function name
arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII
dt-bindings: net: sun8i-emac: Add A100 EMAC compatible
arm64: dts: allwinner: a100: Add EMAC support
arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support
.../net/allwinner,sun8i-a83t-emac.yaml | 1 +
.../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 35 +++++++++++++++++++
.../sun50i-a133-liontron-h-a133l.dts | 19 ++++++++++
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++---------
4 files changed, 71 insertions(+), 16 deletions(-)
--
2.49.0
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-06-26 8:09 [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support Paul Kocialkowski
@ 2025-06-26 8:09 ` Paul Kocialkowski
2025-06-28 4:39 ` Chen-Yu Tsai
` (2 more replies)
2025-06-26 8:09 ` [PATCH 2/5] arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII Paul Kocialkowski
` (5 subsequent siblings)
6 siblings, 3 replies; 30+ messages in thread
From: Paul Kocialkowski @ 2025-06-26 8:09 UTC (permalink / raw)
To: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio
Cc: Andrew Lunn, David S . Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Linus Walleij,
Andre Przywara, Paul Kocialkowski
The Allwinner A100/A133 only has a single emac instance, which is
referred to as "emac" everywhere. Fix the pin names to drop the
trailing "0" that has no reason to be.
Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
---
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
index b97de80ae2f3..95b764ee1c0d 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
@@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
- SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
+ SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
- SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
+ SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
- SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
+ SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
- SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
+ SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart3"), /* TX */
SUNXI_FUNCTION(0x3, "spi1"), /* CS */
- SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
+ SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
SUNXI_FUNCTION(0x2, "uart3"), /* RX */
SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
SUNXI_FUNCTION(0x4, "ledc"),
- SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
+ SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
- SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
+ SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
- SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
+ SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
- SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
+ SUNXI_FUNCTION(0x5, "emac"), /* MDC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
- SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
+ SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
- SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
+ SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
- SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
+ SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
- SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
+ SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
- SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
+ SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
- SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
+ SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
- SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
+ SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
--
2.49.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 2/5] arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII
2025-06-26 8:09 [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support Paul Kocialkowski
2025-06-26 8:09 ` [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name Paul Kocialkowski
@ 2025-06-26 8:09 ` Paul Kocialkowski
2025-07-04 22:45 ` Andre Przywara
2025-06-26 8:09 ` [PATCH 3/5] dt-bindings: net: sun8i-emac: Add A100 EMAC compatible Paul Kocialkowski
` (4 subsequent siblings)
6 siblings, 1 reply; 30+ messages in thread
From: Paul Kocialkowski @ 2025-06-26 8:09 UTC (permalink / raw)
To: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio
Cc: Andrew Lunn, David S . Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Linus Walleij,
Andre Przywara, Paul Kocialkowski
The Allwinner A100/A133 supports both RGMII and RMII for its Ethernet
MAC (EMAC) controller. Add corresponding pin definitions.
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index bd366389b238..1c4e71b32911 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -236,6 +236,21 @@ mmc2_pins: mmc2-pins {
bias-pull-up;
};
+ rgmii_pins: rgmii-pins {
+ pins = "PH0", "PH1", "PH2", "PH3", "PH4",
+ "PH5", "PH6", "PH7", "PH9", "PH10",
+ "PH14", "PH15", "PH16", "PH17", "PH18";
+ function = "emac";
+ drive-strength = <40>;
+ };
+
+ rmii_pins: rmii-pins {
+ pins = "PH0", "PH1", "PH2", "PH3", "PH4",
+ "PH5", "PH6", "PH7", "PH9", "PH10";
+ function = "emac";
+ drive-strength = <40>;
+ };
+
uart0_pb_pins: uart0-pb-pins {
pins = "PB9", "PB10";
function = "uart0";
--
2.49.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 3/5] dt-bindings: net: sun8i-emac: Add A100 EMAC compatible
2025-06-26 8:09 [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support Paul Kocialkowski
2025-06-26 8:09 ` [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name Paul Kocialkowski
2025-06-26 8:09 ` [PATCH 2/5] arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII Paul Kocialkowski
@ 2025-06-26 8:09 ` Paul Kocialkowski
2025-06-27 21:21 ` Rob Herring (Arm)
2025-07-04 22:40 ` Andre Przywara
2025-06-26 8:09 ` [PATCH 4/5] arm64: dts: allwinner: a100: Add EMAC support Paul Kocialkowski
` (3 subsequent siblings)
6 siblings, 2 replies; 30+ messages in thread
From: Paul Kocialkowski @ 2025-06-26 8:09 UTC (permalink / raw)
To: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio
Cc: Andrew Lunn, David S . Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Linus Walleij,
Andre Przywara, Paul Kocialkowski
The Allwinner A100/A133 has an Ethernet MAC (EMAC) controller that is
compatible with the A64 one. It features the same syscon registers for
control of the top-level integration of the unit.
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
---
.../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
index 7b6a2fde8175..0ae415f1e69c 100644
--- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
@@ -21,6 +21,7 @@ properties:
- items:
- enum:
- allwinner,sun20i-d1-emac
+ - allwinner,sun50i-a100-emac
- allwinner,sun50i-h6-emac
- allwinner,sun50i-h616-emac0
- allwinner,sun55i-a523-emac0
--
2.49.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 4/5] arm64: dts: allwinner: a100: Add EMAC support
2025-06-26 8:09 [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support Paul Kocialkowski
` (2 preceding siblings ...)
2025-06-26 8:09 ` [PATCH 3/5] dt-bindings: net: sun8i-emac: Add A100 EMAC compatible Paul Kocialkowski
@ 2025-06-26 8:09 ` Paul Kocialkowski
2025-07-04 23:32 ` Andre Przywara
2025-06-26 8:09 ` [PATCH 5/5] arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support Paul Kocialkowski
` (2 subsequent siblings)
6 siblings, 1 reply; 30+ messages in thread
From: Paul Kocialkowski @ 2025-06-26 8:09 UTC (permalink / raw)
To: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio
Cc: Andrew Lunn, David S . Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Linus Walleij,
Andre Przywara, Paul Kocialkowski
The Allwinner A100/A133 Ethernet MAC (EMAC) is compatible with the A64
one and needs access to the syscon register for control of the
top-level integration of the unit.
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
---
.../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index 1c4e71b32911..205faa90d37b 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -420,6 +420,26 @@ i2c3: i2c@5002c00 {
#size-cells = <0>;
};
+ emac: ethernet@5020000 {
+ compatible = "allwinner,sun50i-a100-emac",
+ "allwinner,sun50i-a64-emac";
+ reg = <0x5020000 0x10000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ syscon = <&syscon>;
+ status = "disabled";
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
ths: thermal-sensor@5070400 {
compatible = "allwinner,sun50i-a100-ths";
reg = <0x05070400 0x100>;
--
2.49.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 5/5] arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support
2025-06-26 8:09 [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support Paul Kocialkowski
` (3 preceding siblings ...)
2025-06-26 8:09 ` [PATCH 4/5] arm64: dts: allwinner: a100: Add EMAC support Paul Kocialkowski
@ 2025-06-26 8:09 ` Paul Kocialkowski
2025-06-27 22:40 ` [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support patchwork-bot+netdevbpf
2025-07-04 15:37 ` (subset) " Chen-Yu Tsai
6 siblings, 0 replies; 30+ messages in thread
From: Paul Kocialkowski @ 2025-06-26 8:09 UTC (permalink / raw)
To: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio
Cc: Andrew Lunn, David S . Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Linus Walleij,
Andre Przywara, Paul Kocialkowski
The Liontron H-A133L board features an Ethernet controller with a
JLSemi JL1101 PHY. Its reset pin is tied to the PH12 GPIO.
Note that the reset pin must be handled as a bus-wide reset GPIO in
order to let the MDIO core properly reset it before trying to read
its identification registers. There's no other device on the MDIO bus.
The datasheet of the PHY mentions that the reset signal must be held
for 1 ms to take effect. Make it 2 ms (and the same for post-delay) to
be on the safe side without wasting too much time during boot.
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
---
.../sun50i-a133-liontron-h-a133l.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts b/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts
index fe77178d3e33..04dd7f781894 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts
@@ -65,6 +65,25 @@ &ehci1 {
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ phy-handle = <&rmii_phy>;
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&mdio {
+ reset-gpios = <&pio 7 12 GPIO_ACTIVE_LOW>; /* PH12 */
+ reset-delay-us = <2000>;
+ reset-post-delay-us = <2000>;
+
+ rmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
--
2.49.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH 3/5] dt-bindings: net: sun8i-emac: Add A100 EMAC compatible
2025-06-26 8:09 ` [PATCH 3/5] dt-bindings: net: sun8i-emac: Add A100 EMAC compatible Paul Kocialkowski
@ 2025-06-27 21:21 ` Rob Herring (Arm)
2025-07-04 22:40 ` Andre Przywara
1 sibling, 0 replies; 30+ messages in thread
From: Rob Herring (Arm) @ 2025-06-27 21:21 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: Conor Dooley, linux-kernel, devicetree, Paolo Abeni, Chen-Yu Tsai,
Andrew Lunn, netdev, linux-arm-kernel, Andre Przywara,
David S . Miller, Jernej Skrabec, Krzysztof Kozlowski,
Eric Dumazet, Samuel Holland, linux-sunxi, linux-gpio,
Linus Walleij, Jakub Kicinski
On Thu, 26 Jun 2025 10:09:21 +0200, Paul Kocialkowski wrote:
> The Allwinner A100/A133 has an Ethernet MAC (EMAC) controller that is
> compatible with the A64 one. It features the same syscon registers for
> control of the top-level integration of the unit.
>
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> ---
> .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support
2025-06-26 8:09 [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support Paul Kocialkowski
` (4 preceding siblings ...)
2025-06-26 8:09 ` [PATCH 5/5] arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support Paul Kocialkowski
@ 2025-06-27 22:40 ` patchwork-bot+netdevbpf
2025-07-04 15:37 ` (subset) " Chen-Yu Tsai
6 siblings, 0 replies; 30+ messages in thread
From: patchwork-bot+netdevbpf @ 2025-06-27 22:40 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio, andrew+netdev, davem, edumazet, kuba, pabeni, robh,
krzk+dt, conor+dt, wens, jernej.skrabec, samuel, linus.walleij,
andre.przywara
Hello:
This series was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Thu, 26 Jun 2025 10:09:18 +0200 you wrote:
> This series adds support for the Alwinner A100/A133 Ethernet MAC (EMAC)
> and uses it in the Liontron H-A133L board.
>
> Paul Kocialkowski (5):
> pinctrl: sunxi: Fix a100 emac pin function name
> arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII
> dt-bindings: net: sun8i-emac: Add A100 EMAC compatible
> arm64: dts: allwinner: a100: Add EMAC support
> arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support
>
> [...]
Here is the summary with links:
- [1/5] pinctrl: sunxi: Fix a100 emac pin function name
(no matching commit)
- [2/5] arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII
(no matching commit)
- [3/5] dt-bindings: net: sun8i-emac: Add A100 EMAC compatible
https://git.kernel.org/netdev/net-next/c/0a12c435a1d6
- [4/5] arm64: dts: allwinner: a100: Add EMAC support
(no matching commit)
- [5/5] arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support
(no matching commit)
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-06-26 8:09 ` [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name Paul Kocialkowski
@ 2025-06-28 4:39 ` Chen-Yu Tsai
2025-07-04 8:02 ` Linus Walleij
2025-07-04 22:35 ` Andre Przywara
2 siblings, 0 replies; 30+ messages in thread
From: Chen-Yu Tsai @ 2025-06-28 4:39 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jernej Skrabec, Samuel Holland, Linus Walleij,
Andre Przywara
On Thu, Jun 26, 2025 at 4:10 PM Paul Kocialkowski <paulk@sys-base.io> wrote:
>
> The Allwinner A100/A133 only has a single emac instance, which is
> referred to as "emac" everywhere. Fix the pin names to drop the
> trailing "0" that has no reason to be.
>
> Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-06-26 8:09 ` [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name Paul Kocialkowski
2025-06-28 4:39 ` Chen-Yu Tsai
@ 2025-07-04 8:02 ` Linus Walleij
2025-07-04 22:35 ` Andre Przywara
2 siblings, 0 replies; 30+ messages in thread
From: Linus Walleij @ 2025-07-04 8:02 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Andre Przywara
On Thu, Jun 26, 2025 at 10:11 AM Paul Kocialkowski <paulk@sys-base.io> wrote:
> The Allwinner A100/A133 only has a single emac instance, which is
> referred to as "emac" everywhere. Fix the pin names to drop the
> trailing "0" that has no reason to be.
>
> Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
This patch 1/5 applied to the pin control tree.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: (subset) [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support
2025-06-26 8:09 [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support Paul Kocialkowski
` (5 preceding siblings ...)
2025-06-27 22:40 ` [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support patchwork-bot+netdevbpf
@ 2025-07-04 15:37 ` Chen-Yu Tsai
6 siblings, 0 replies; 30+ messages in thread
From: Chen-Yu Tsai @ 2025-07-04 15:37 UTC (permalink / raw)
To: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio, Paul Kocialkowski
Cc: Andrew Lunn, David S . Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jernej Skrabec, Samuel Holland, Linus Walleij, Andre Przywara
On Thu, 26 Jun 2025 10:09:18 +0200, Paul Kocialkowski wrote:
> This series adds support for the Alwinner A100/A133 Ethernet MAC (EMAC)
> and uses it in the Liontron H-A133L board.
>
> Paul Kocialkowski (5):
> pinctrl: sunxi: Fix a100 emac pin function name
> arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII
> dt-bindings: net: sun8i-emac: Add A100 EMAC compatible
> arm64: dts: allwinner: a100: Add EMAC support
> arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support
>
> [...]
Applied to sunxi/dt-for-6.17 in local tree, thanks!
[2/5] arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII
commit: e8ce8507ecac5c4125e8d8aca147cbd7d3eae573
[4/5] arm64: dts: allwinner: a100: Add EMAC support
commit: ce51ff18daca21723f97d22477416418dcfca8dc
[5/5] arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support
commit: 1c5f20ebc46d9cf5fd19c343537de15aeeda2d36
Best regards,
--
Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-06-26 8:09 ` [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name Paul Kocialkowski
2025-06-28 4:39 ` Chen-Yu Tsai
2025-07-04 8:02 ` Linus Walleij
@ 2025-07-04 22:35 ` Andre Przywara
2025-07-05 14:38 ` Andre Przywara
2025-07-05 23:52 ` Paul Kocialkowski
2 siblings, 2 replies; 30+ messages in thread
From: Andre Przywara @ 2025-07-04 22:35 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Linus Walleij
On Thu, 26 Jun 2025 10:09:19 +0200
Paul Kocialkowski <paulk@sys-base.io> wrote:
Hi Paul,
> The Allwinner A100/A133 only has a single emac instance, which is
> referred to as "emac" everywhere. Fix the pin names to drop the
> trailing "0" that has no reason to be.
Sorry, but this is wrong. There *is* a second EMAC on the A133 die: it's
indeed not mentioned in the manual, but you can probe its MMIO
registers (@0x5030000), and there is a second syscon register
(@0x03000034). It's mentioned in several BSP code places ([1]).
It seem like no suitable pins are connected on the A133
package, but that should not affect the A100 .dtsi (we use a similar
approach for the H616 and A523).
So I think we should keep the emac0 name.
Cheers,
Andre
[1]
https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
>
> Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> ---
> drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> index b97de80ae2f3..95b764ee1c0d 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> SUNXI_FUNCTION(0x4, "ledc"),
> - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> SUNXI_FUNCTION(0x0, "gpio_in"),
> @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> SUNXI_FUNCTION(0x0, "gpio_in"),
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/5] dt-bindings: net: sun8i-emac: Add A100 EMAC compatible
2025-06-26 8:09 ` [PATCH 3/5] dt-bindings: net: sun8i-emac: Add A100 EMAC compatible Paul Kocialkowski
2025-06-27 21:21 ` Rob Herring (Arm)
@ 2025-07-04 22:40 ` Andre Przywara
1 sibling, 0 replies; 30+ messages in thread
From: Andre Przywara @ 2025-07-04 22:40 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Linus Walleij
On Thu, 26 Jun 2025 10:09:21 +0200
Paul Kocialkowski <paulk@sys-base.io> wrote:
Hi,
> The Allwinner A100/A133 has an Ethernet MAC (EMAC) controller that is
> compatible with the A64 one. It features the same syscon registers for
> control of the top-level integration of the unit.
As mentioned, the A133 has two Ethernet MACs on its die. Both look
compatible to the A64, but EMAC1 uses a separate syscon register
(@+0x34), so needs a separate compatible string for that one. We don't
seem to have an example of any board (or even SoC package) that uses
the 2nd EMAC, but I suggest to not slam the door on that possibility,
and use a name suffixed by "0": allwinner,sun50i-a100-emac0. There is
precedence for that in the H616 case.
Otherwise I can confirm that the EMAC is indeed compatible to the A64,
so with that fixed:
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
>
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> ---
> .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> index 7b6a2fde8175..0ae415f1e69c 100644
> --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> @@ -21,6 +21,7 @@ properties:
> - items:
> - enum:
> - allwinner,sun20i-d1-emac
> + - allwinner,sun50i-a100-emac
> - allwinner,sun50i-h6-emac
> - allwinner,sun50i-h616-emac0
> - allwinner,sun55i-a523-emac0
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 2/5] arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII
2025-06-26 8:09 ` [PATCH 2/5] arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII Paul Kocialkowski
@ 2025-07-04 22:45 ` Andre Przywara
0 siblings, 0 replies; 30+ messages in thread
From: Andre Przywara @ 2025-07-04 22:45 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Linus Walleij
On Thu, 26 Jun 2025 10:09:20 +0200
Paul Kocialkowski <paulk@sys-base.io> wrote:
Hi,
> The Allwinner A100/A133 supports both RGMII and RMII for its Ethernet
> MAC (EMAC) controller. Add corresponding pin definitions.
Apart from suffixing everything with "0" ("rgmii0_pins: rgmii0-pins"),
this matches exactly what I gathered from manual and tested in my own
version of this patch a few weeks ago, so with the 0 suffix attached:
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
>
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> index bd366389b238..1c4e71b32911 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -236,6 +236,21 @@ mmc2_pins: mmc2-pins {
> bias-pull-up;
> };
>
> + rgmii_pins: rgmii-pins {
> + pins = "PH0", "PH1", "PH2", "PH3", "PH4",
> + "PH5", "PH6", "PH7", "PH9", "PH10",
> + "PH14", "PH15", "PH16", "PH17", "PH18";
> + function = "emac";
> + drive-strength = <40>;
> + };
> +
> + rmii_pins: rmii-pins {
> + pins = "PH0", "PH1", "PH2", "PH3", "PH4",
> + "PH5", "PH6", "PH7", "PH9", "PH10";
> + function = "emac";
> + drive-strength = <40>;
> + };
> +
> uart0_pb_pins: uart0-pb-pins {
> pins = "PB9", "PB10";
> function = "uart0";
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 4/5] arm64: dts: allwinner: a100: Add EMAC support
2025-06-26 8:09 ` [PATCH 4/5] arm64: dts: allwinner: a100: Add EMAC support Paul Kocialkowski
@ 2025-07-04 23:32 ` Andre Przywara
0 siblings, 0 replies; 30+ messages in thread
From: Andre Przywara @ 2025-07-04 23:32 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Linus Walleij
On Thu, 26 Jun 2025 10:09:22 +0200
Paul Kocialkowski <paulk@sys-base.io> wrote:
Hi,
> The Allwinner A100/A133 Ethernet MAC (EMAC) is compatible with the A64
> one and needs access to the syscon register for control of the
> top-level integration of the unit.
as mentioned before, this would benefit from using "emac0", to signify
that there is a second MAC, but otherwise this matches what I found in
the manual and could test, so with the 0 suffix added:
>
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
> .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 20 +++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> index 1c4e71b32911..205faa90d37b 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -420,6 +420,26 @@ i2c3: i2c@5002c00 {
> #size-cells = <0>;
> };
>
> + emac: ethernet@5020000 {
> + compatible = "allwinner,sun50i-a100-emac",
> + "allwinner,sun50i-a64-emac";
> + reg = <0x5020000 0x10000>;
> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + clocks = <&ccu CLK_BUS_EMAC>;
> + clock-names = "stmmaceth";
> + resets = <&ccu RST_BUS_EMAC>;
> + reset-names = "stmmaceth";
> + syscon = <&syscon>;
> + status = "disabled";
> +
> + mdio: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> ths: thermal-sensor@5070400 {
> compatible = "allwinner,sun50i-a100-ths";
> reg = <0x05070400 0x100>;
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-07-04 22:35 ` Andre Przywara
@ 2025-07-05 14:38 ` Andre Przywara
2025-07-06 0:00 ` Paul Kocialkowski
2025-07-05 23:52 ` Paul Kocialkowski
1 sibling, 1 reply; 30+ messages in thread
From: Andre Przywara @ 2025-07-05 14:38 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Linus Walleij
On Fri, 4 Jul 2025 23:35:35 +0100
Andre Przywara <andre.przywara@arm.com> wrote:
Hi,
> On Thu, 26 Jun 2025 10:09:19 +0200
> Paul Kocialkowski <paulk@sys-base.io> wrote:
>
> Hi Paul,
>
> > The Allwinner A100/A133 only has a single emac instance, which is
> > referred to as "emac" everywhere. Fix the pin names to drop the
> > trailing "0" that has no reason to be.
>
> Sorry, but this is wrong. There *is* a second EMAC on the A133 die: it's
> indeed not mentioned in the manual, but you can probe its MMIO
> registers (@0x5030000), and there is a second syscon register
> (@0x03000034). It's mentioned in several BSP code places ([1]).
> It seem like no suitable pins are connected on the A133
> package, but that should not affect the A100 .dtsi (we use a similar
> approach for the H616 and A523).
>
> So I think we should keep the emac0 name.
just thinking that it's even worse: this changes the DT visible pinctrl
function name, so it's a DT ABI change. With the "emac0" function name,
Ethernet would work with stable kernels already (as everything is
compatible, it's just about DT changes). But with this change, pinctrl
drivers in older kernels would not match.
So I would very much like to see this patch moved out. Is it just in
LinusW's tree so far? I don't see it in -next yet.
Cheers,
Andre.
> [1]
> https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
>
>
> >
> > Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> > ---
> > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> > 1 file changed, 16 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > index b97de80ae2f3..95b764ee1c0d 100644
> > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> > SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> > + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> > SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> > SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> > SUNXI_FUNCTION(0x4, "ledc"),
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> > SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> > SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> > SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> > SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> > SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> > + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> > SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> > SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> > + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> > SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> > + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> > SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> > SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> > SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> > SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-07-04 22:35 ` Andre Przywara
2025-07-05 14:38 ` Andre Przywara
@ 2025-07-05 23:52 ` Paul Kocialkowski
1 sibling, 0 replies; 30+ messages in thread
From: Paul Kocialkowski @ 2025-07-05 23:52 UTC (permalink / raw)
To: Andre Przywara
Cc: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Linus Walleij
[-- Attachment #1: Type: text/plain, Size: 9032 bytes --]
Hi Andre,
Le Fri 04 Jul 25, 23:35, Andre Przywara a écrit :
> On Thu, 26 Jun 2025 10:09:19 +0200
> Paul Kocialkowski <paulk@sys-base.io> wrote:
>
> Hi Paul,
>
> > The Allwinner A100/A133 only has a single emac instance, which is
> > referred to as "emac" everywhere. Fix the pin names to drop the
> > trailing "0" that has no reason to be.
>
> Sorry, but this is wrong. There *is* a second EMAC on the A133 die: it's
> indeed not mentioned in the manual, but you can probe its MMIO
> registers (@0x5030000), and there is a second syscon register
> (@0x03000034). It's mentioned in several BSP code places ([1]).
Okay so I looked a bit closer at this and everything hints that you are right.
Not the first time Allwinner puts a bunch more blocks into the die and doesn't
talk about it. For example the H3 has an ISP block but it is not mentionned
anywhere.
It seems that most packages of the sun50iw10 die don't expose the second EMAC
controller, but I found some brief info about T509 that indicates it has both
EMACs exposed at http://rpdzkj.com/copy_2_2198291_151408_4727683.html
As far as I know the packages are: A100, A133, A133P, A53, T509, R818 and
MR813/MR813B.
So yes it seems this was a bad decision, sorry about that.
I will send some revert patches for the whole thing then.
> It seem like no suitable pins are connected on the A133
> package, but that should not affect the A100 .dtsi (we use a similar
> approach for the H616 and A523).
Yes it makes sense to have the most common dtsi file concern the whole die.
Thanks,
Paul
> So I think we should keep the emac0 name.
>
> Cheers,
> Andre
>
>
> [1]
> https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
>
>
> >
> > Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> > ---
> > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> > 1 file changed, 16 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > index b97de80ae2f3..95b764ee1c0d 100644
> > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> > SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> > + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> > SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> > SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> > SUNXI_FUNCTION(0x4, "ledc"),
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> > SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> > SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> > SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> > SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> > SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> > + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> > SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> > SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> > + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> > SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> > + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> > SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> > SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> > SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> > SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
>
--
Paul Kocialkowski,
Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/
Expert in multimedia, graphics and embedded hardware support with Linux.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-07-05 14:38 ` Andre Przywara
@ 2025-07-06 0:00 ` Paul Kocialkowski
2025-07-06 15:04 ` Chen-Yu Tsai
0 siblings, 1 reply; 30+ messages in thread
From: Paul Kocialkowski @ 2025-07-06 0:00 UTC (permalink / raw)
To: Andre Przywara
Cc: netdev, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-gpio, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Linus Walleij
[-- Attachment #1: Type: text/plain, Size: 9716 bytes --]
Hi Andre,
Le Sat 05 Jul 25, 15:38, Andre Przywara a écrit :
> On Fri, 4 Jul 2025 23:35:35 +0100
> Andre Przywara <andre.przywara@arm.com> wrote:
>
> Hi,
>
> > On Thu, 26 Jun 2025 10:09:19 +0200
> > Paul Kocialkowski <paulk@sys-base.io> wrote:
> >
> > Hi Paul,
> >
> > > The Allwinner A100/A133 only has a single emac instance, which is
> > > referred to as "emac" everywhere. Fix the pin names to drop the
> > > trailing "0" that has no reason to be.
> >
> > Sorry, but this is wrong. There *is* a second EMAC on the A133 die: it's
> > indeed not mentioned in the manual, but you can probe its MMIO
> > registers (@0x5030000), and there is a second syscon register
> > (@0x03000034). It's mentioned in several BSP code places ([1]).
> > It seem like no suitable pins are connected on the A133
> > package, but that should not affect the A100 .dtsi (we use a similar
> > approach for the H616 and A523).
> >
> > So I think we should keep the emac0 name.
>
> just thinking that it's even worse: this changes the DT visible pinctrl
> function name, so it's a DT ABI change. With the "emac0" function name,
> Ethernet would work with stable kernels already (as everything is
> compatible, it's just about DT changes). But with this change, pinctrl
> drivers in older kernels would not match.
Given that the port is still very early and experimental and has very few users
and no field deployment so I don't really think it would have annoyed anybody in
practice. But yes in principle you are right, while the header renames keep the
same value, the string names are used to match the device-tree definitions and
this constitues ABI that needs to remain stable.
> So I would very much like to see this patch moved out. Is it just in
> LinusW's tree so far? I don't see it in -next yet.
I don't think the patches were accepted for over a week so we can probably
still act. I will send reverts, unless maintainers want to manually remove
these commits?
Cheers,
Paul
> Cheers,
> Andre.
>
> > [1]
> > https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
> >
> >
> > >
> > > Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> > > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> > > ---
> > > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> > > 1 file changed, 16 insertions(+), 16 deletions(-)
> > >
> > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > index b97de80ae2f3..95b764ee1c0d 100644
> > > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> > > SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> > > SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> > > SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> > > SUNXI_FUNCTION(0x4, "ledc"),
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> > > SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> > > SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> > > SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> > > SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> > > SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> > > SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> > > SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> > > SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> > > SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> > > SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> > > SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> > > SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> > > SUNXI_FUNCTION(0x0, "gpio_in"),
> >
> >
>
--
Paul Kocialkowski,
Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/
Expert in multimedia, graphics and embedded hardware support with Linux.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-07-06 0:00 ` Paul Kocialkowski
@ 2025-07-06 15:04 ` Chen-Yu Tsai
2025-07-07 3:07 ` Chen-Yu Tsai
` (2 more replies)
0 siblings, 3 replies; 30+ messages in thread
From: Chen-Yu Tsai @ 2025-07-06 15:04 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: Andre Przywara, netdev, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec, Samuel Holland,
Linus Walleij
On Sun, Jul 6, 2025 at 8:00 AM Paul Kocialkowski <paulk@sys-base.io> wrote:
>
> Hi Andre,
>
> Le Sat 05 Jul 25, 15:38, Andre Przywara a écrit :
> > On Fri, 4 Jul 2025 23:35:35 +0100
> > Andre Przywara <andre.przywara@arm.com> wrote:
> >
> > Hi,
> >
> > > On Thu, 26 Jun 2025 10:09:19 +0200
> > > Paul Kocialkowski <paulk@sys-base.io> wrote:
> > >
> > > Hi Paul,
> > >
> > > > The Allwinner A100/A133 only has a single emac instance, which is
> > > > referred to as "emac" everywhere. Fix the pin names to drop the
> > > > trailing "0" that has no reason to be.
> > >
> > > Sorry, but this is wrong. There *is* a second EMAC on the A133 die: it's
> > > indeed not mentioned in the manual, but you can probe its MMIO
> > > registers (@0x5030000), and there is a second syscon register
> > > (@0x03000034). It's mentioned in several BSP code places ([1]).
> > > It seem like no suitable pins are connected on the A133
> > > package, but that should not affect the A100 .dtsi (we use a similar
> > > approach for the H616 and A523).
> > >
> > > So I think we should keep the emac0 name.
> >
> > just thinking that it's even worse: this changes the DT visible pinctrl
> > function name, so it's a DT ABI change. With the "emac0" function name,
> > Ethernet would work with stable kernels already (as everything is
> > compatible, it's just about DT changes). But with this change, pinctrl
> > drivers in older kernels would not match.
>
> Given that the port is still very early and experimental and has very few users
> and no field deployment so I don't really think it would have annoyed anybody in
> practice. But yes in principle you are right, while the header renames keep the
> same value, the string names are used to match the device-tree definitions and
> this constitues ABI that needs to remain stable.
>
> > So I would very much like to see this patch moved out. Is it just in
> > LinusW's tree so far? I don't see it in -next yet.
>
> I don't think the patches were accepted for over a week so we can probably
> still act. I will send reverts, unless maintainers want to manually remove
> these commits?
I can drop the dts patches from the sunxi tree. Linus might be able to
drop the pinctrl patch.
You definitely need to send a revert for the DT binding patch that is
already in net-next.
ChenYu
> Cheers,
>
> Paul
>
> > Cheers,
> > Andre.
> >
> > > [1]
> > > https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
> > >
> > >
> > > >
> > > > Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> > > > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> > > > ---
> > > > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> > > > 1 file changed, 16 insertions(+), 16 deletions(-)
> > > >
> > > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > index b97de80ae2f3..95b764ee1c0d 100644
> > > > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> > > > SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> > > > SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> > > > SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> > > > SUNXI_FUNCTION(0x4, "ledc"),
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> > > > SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> > > > SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> > > > SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> > > > SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> > > > SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> > > > SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> > > > SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> > > > SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> > > > SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> > > > SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> > > > SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> > > > SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > >
> > >
> >
>
> --
> Paul Kocialkowski,
>
> Independent contractor - sys-base - https://www.sys-base.io/
> Free software developer - https://www.paulk.fr/
>
> Expert in multimedia, graphics and embedded hardware support with Linux.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-07-06 15:04 ` Chen-Yu Tsai
@ 2025-07-07 3:07 ` Chen-Yu Tsai
2025-07-07 9:40 ` Paul Kocialkowski
2025-07-07 9:39 ` Paul Kocialkowski
2025-07-11 18:13 ` Linus Walleij
2 siblings, 1 reply; 30+ messages in thread
From: Chen-Yu Tsai @ 2025-07-07 3:07 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: Andre Przywara, netdev, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec, Samuel Holland,
Linus Walleij
On Sun, Jul 6, 2025 at 11:04 PM Chen-Yu Tsai <wens@csie.org> wrote:
>
> On Sun, Jul 6, 2025 at 8:00 AM Paul Kocialkowski <paulk@sys-base.io> wrote:
> >
> > Hi Andre,
> >
> > Le Sat 05 Jul 25, 15:38, Andre Przywara a écrit :
> > > On Fri, 4 Jul 2025 23:35:35 +0100
> > > Andre Przywara <andre.przywara@arm.com> wrote:
> > >
> > > Hi,
> > >
> > > > On Thu, 26 Jun 2025 10:09:19 +0200
> > > > Paul Kocialkowski <paulk@sys-base.io> wrote:
> > > >
> > > > Hi Paul,
> > > >
> > > > > The Allwinner A100/A133 only has a single emac instance, which is
> > > > > referred to as "emac" everywhere. Fix the pin names to drop the
> > > > > trailing "0" that has no reason to be.
> > > >
> > > > Sorry, but this is wrong. There *is* a second EMAC on the A133 die: it's
> > > > indeed not mentioned in the manual, but you can probe its MMIO
> > > > registers (@0x5030000), and there is a second syscon register
> > > > (@0x03000034). It's mentioned in several BSP code places ([1]).
> > > > It seem like no suitable pins are connected on the A133
> > > > package, but that should not affect the A100 .dtsi (we use a similar
> > > > approach for the H616 and A523).
> > > >
> > > > So I think we should keep the emac0 name.
> > >
> > > just thinking that it's even worse: this changes the DT visible pinctrl
> > > function name, so it's a DT ABI change. With the "emac0" function name,
> > > Ethernet would work with stable kernels already (as everything is
> > > compatible, it's just about DT changes). But with this change, pinctrl
> > > drivers in older kernels would not match.
> >
> > Given that the port is still very early and experimental and has very few users
> > and no field deployment so I don't really think it would have annoyed anybody in
> > practice. But yes in principle you are right, while the header renames keep the
> > same value, the string names are used to match the device-tree definitions and
> > this constitues ABI that needs to remain stable.
> >
> > > So I would very much like to see this patch moved out. Is it just in
> > > LinusW's tree so far? I don't see it in -next yet.
> >
> > I don't think the patches were accepted for over a week so we can probably
> > still act. I will send reverts, unless maintainers want to manually remove
> > these commits?
>
> I can drop the dts patches from the sunxi tree. Linus might be able to
> drop the pinctrl patch.
FYI I dropped the dts patches for now, though I forgot to redo the -next
branch last night, so today's linux-next might not reflect it.
ChenYu
> You definitely need to send a revert for the DT binding patch that is
> already in net-next.
>
>
> ChenYu
>
>
> > Cheers,
> >
> > Paul
> >
> > > Cheers,
> > > Andre.
> > >
> > > > [1]
> > > > https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
> > > >
> > > >
> > > > >
> > > > > Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> > > > > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> > > > > ---
> > > > > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> > > > > 1 file changed, 16 insertions(+), 16 deletions(-)
> > > > >
> > > > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > index b97de80ae2f3..95b764ee1c0d 100644
> > > > > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> > > > > SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> > > > > SUNXI_FUNCTION(0x4, "ledc"),
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> > > > > SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> > > > > SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> > > > > SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> > > > > SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> > > > > SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> > > > > SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> > > > > SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > >
> > > >
> > >
> >
> > --
> > Paul Kocialkowski,
> >
> > Independent contractor - sys-base - https://www.sys-base.io/
> > Free software developer - https://www.paulk.fr/
> >
> > Expert in multimedia, graphics and embedded hardware support with Linux.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-07-06 15:04 ` Chen-Yu Tsai
2025-07-07 3:07 ` Chen-Yu Tsai
@ 2025-07-07 9:39 ` Paul Kocialkowski
2025-07-07 9:52 ` Chen-Yu Tsai
2025-07-11 18:13 ` Linus Walleij
2 siblings, 1 reply; 30+ messages in thread
From: Paul Kocialkowski @ 2025-07-07 9:39 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Andre Przywara, netdev, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec, Samuel Holland,
Linus Walleij
[-- Attachment #1: Type: text/plain, Size: 13101 bytes --]
Hi Chen-Yu,
Le Sun 06 Jul 25, 23:04, Chen-Yu Tsai a écrit :
> On Sun, Jul 6, 2025 at 8:00 AM Paul Kocialkowski <paulk@sys-base.io> wrote:
> >
> > Hi Andre,
> >
> > Le Sat 05 Jul 25, 15:38, Andre Przywara a écrit :
> > > On Fri, 4 Jul 2025 23:35:35 +0100
> > > Andre Przywara <andre.przywara@arm.com> wrote:
> > >
> > > Hi,
> > >
> > > > On Thu, 26 Jun 2025 10:09:19 +0200
> > > > Paul Kocialkowski <paulk@sys-base.io> wrote:
> > > >
> > > > Hi Paul,
> > > >
> > > > > The Allwinner A100/A133 only has a single emac instance, which is
> > > > > referred to as "emac" everywhere. Fix the pin names to drop the
> > > > > trailing "0" that has no reason to be.
> > > >
> > > > Sorry, but this is wrong. There *is* a second EMAC on the A133 die: it's
> > > > indeed not mentioned in the manual, but you can probe its MMIO
> > > > registers (@0x5030000), and there is a second syscon register
> > > > (@0x03000034). It's mentioned in several BSP code places ([1]).
> > > > It seem like no suitable pins are connected on the A133
> > > > package, but that should not affect the A100 .dtsi (we use a similar
> > > > approach for the H616 and A523).
> > > >
> > > > So I think we should keep the emac0 name.
> > >
> > > just thinking that it's even worse: this changes the DT visible pinctrl
> > > function name, so it's a DT ABI change. With the "emac0" function name,
> > > Ethernet would work with stable kernels already (as everything is
> > > compatible, it's just about DT changes). But with this change, pinctrl
> > > drivers in older kernels would not match.
> >
> > Given that the port is still very early and experimental and has very few users
> > and no field deployment so I don't really think it would have annoyed anybody in
> > practice. But yes in principle you are right, while the header renames keep the
> > same value, the string names are used to match the device-tree definitions and
> > this constitues ABI that needs to remain stable.
> >
> > > So I would very much like to see this patch moved out. Is it just in
> > > LinusW's tree so far? I don't see it in -next yet.
> >
> > I don't think the patches were accepted for over a week so we can probably
> > still act. I will send reverts, unless maintainers want to manually remove
> > these commits?
>
> I can drop the dts patches from the sunxi tree. Linus might be able to
> drop the pinctrl patch.
>
> You definitely need to send a revert for the DT binding patch that is
> already in net-next.
Should this really affect the bindings though?
From what Andre reported, both EMAC0 and EMAC1 should be the same block so it
doesn't seem particularly necessary to have a different compatible.
Looking at Allwiner's BSP code for the A133[0], I don't see any difference
between the two. While there's device_type property in Allwinner's dt, it's
apparently not used by the driver[1].
So I think we're still fine with a single compatible (without the controller
index in it).
[0]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi#L2016
[1]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/drivers/net/ethernet/allwinner/sunxi-gmac.c
All the best,
Paul
>
> ChenYu
>
>
> > Cheers,
> >
> > Paul
> >
> > > Cheers,
> > > Andre.
> > >
> > > > [1]
> > > > https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
> > > >
> > > >
> > > > >
> > > > > Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> > > > > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> > > > > ---
> > > > > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> > > > > 1 file changed, 16 insertions(+), 16 deletions(-)
> > > > >
> > > > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > index b97de80ae2f3..95b764ee1c0d 100644
> > > > > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> > > > > SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> > > > > SUNXI_FUNCTION(0x4, "ledc"),
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> > > > > SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> > > > > SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> > > > > SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> > > > > SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> > > > > SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> > > > > SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> > > > > SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > >
> > > >
> > >
> >
> > --
> > Paul Kocialkowski,
> >
> > Independent contractor - sys-base - https://www.sys-base.io/
> > Free software developer - https://www.paulk.fr/
> >
> > Expert in multimedia, graphics and embedded hardware support with Linux.
--
Paul Kocialkowski,
Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/
Expert in multimedia, graphics and embedded hardware support with Linux.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-07-07 3:07 ` Chen-Yu Tsai
@ 2025-07-07 9:40 ` Paul Kocialkowski
0 siblings, 0 replies; 30+ messages in thread
From: Paul Kocialkowski @ 2025-07-07 9:40 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Andre Przywara, netdev, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec, Samuel Holland,
Linus Walleij
[-- Attachment #1: Type: text/plain, Size: 13055 bytes --]
Hi Chen-Yu,
Le Mon 07 Jul 25, 11:07, Chen-Yu Tsai a écrit :
> On Sun, Jul 6, 2025 at 11:04 PM Chen-Yu Tsai <wens@csie.org> wrote:
> >
> > On Sun, Jul 6, 2025 at 8:00 AM Paul Kocialkowski <paulk@sys-base.io> wrote:
> > >
> > > Hi Andre,
> > >
> > > Le Sat 05 Jul 25, 15:38, Andre Przywara a écrit :
> > > > On Fri, 4 Jul 2025 23:35:35 +0100
> > > > Andre Przywara <andre.przywara@arm.com> wrote:
> > > >
> > > > Hi,
> > > >
> > > > > On Thu, 26 Jun 2025 10:09:19 +0200
> > > > > Paul Kocialkowski <paulk@sys-base.io> wrote:
> > > > >
> > > > > Hi Paul,
> > > > >
> > > > > > The Allwinner A100/A133 only has a single emac instance, which is
> > > > > > referred to as "emac" everywhere. Fix the pin names to drop the
> > > > > > trailing "0" that has no reason to be.
> > > > >
> > > > > Sorry, but this is wrong. There *is* a second EMAC on the A133 die: it's
> > > > > indeed not mentioned in the manual, but you can probe its MMIO
> > > > > registers (@0x5030000), and there is a second syscon register
> > > > > (@0x03000034). It's mentioned in several BSP code places ([1]).
> > > > > It seem like no suitable pins are connected on the A133
> > > > > package, but that should not affect the A100 .dtsi (we use a similar
> > > > > approach for the H616 and A523).
> > > > >
> > > > > So I think we should keep the emac0 name.
> > > >
> > > > just thinking that it's even worse: this changes the DT visible pinctrl
> > > > function name, so it's a DT ABI change. With the "emac0" function name,
> > > > Ethernet would work with stable kernels already (as everything is
> > > > compatible, it's just about DT changes). But with this change, pinctrl
> > > > drivers in older kernels would not match.
> > >
> > > Given that the port is still very early and experimental and has very few users
> > > and no field deployment so I don't really think it would have annoyed anybody in
> > > practice. But yes in principle you are right, while the header renames keep the
> > > same value, the string names are used to match the device-tree definitions and
> > > this constitues ABI that needs to remain stable.
> > >
> > > > So I would very much like to see this patch moved out. Is it just in
> > > > LinusW's tree so far? I don't see it in -next yet.
> > >
> > > I don't think the patches were accepted for over a week so we can probably
> > > still act. I will send reverts, unless maintainers want to manually remove
> > > these commits?
> >
> > I can drop the dts patches from the sunxi tree. Linus might be able to
> > drop the pinctrl patch.
>
> FYI I dropped the dts patches for now, though I forgot to redo the -next
> branch last night, so today's linux-next might not reflect it.
Great, thanks for taking care of this!
Paul
> ChenYu
>
> > You definitely need to send a revert for the DT binding patch that is
> > already in net-next.
> >
> >
> > ChenYu
> >
> >
> > > Cheers,
> > >
> > > Paul
> > >
> > > > Cheers,
> > > > Andre.
> > > >
> > > > > [1]
> > > > > https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
> > > > >
> > > > >
> > > > > >
> > > > > > Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> > > > > > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> > > > > > ---
> > > > > > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> > > > > > 1 file changed, 16 insertions(+), 16 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > index b97de80ae2f3..95b764ee1c0d 100644
> > > > > > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> > > > > > SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> > > > > > SUNXI_FUNCTION(0x4, "ledc"),
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> > > > > > SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> > > > > > SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> > > > > > SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> > > > > > SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > >
> > > > >
> > > >
> > >
> > > --
> > > Paul Kocialkowski,
> > >
> > > Independent contractor - sys-base - https://www.sys-base.io/
> > > Free software developer - https://www.paulk.fr/
> > >
> > > Expert in multimedia, graphics and embedded hardware support with Linux.
--
Paul Kocialkowski,
Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/
Expert in multimedia, graphics and embedded hardware support with Linux.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-07-07 9:39 ` Paul Kocialkowski
@ 2025-07-07 9:52 ` Chen-Yu Tsai
2025-07-07 10:13 ` Paul Kocialkowski
0 siblings, 1 reply; 30+ messages in thread
From: Chen-Yu Tsai @ 2025-07-07 9:52 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: Andre Przywara, netdev, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec, Samuel Holland,
Linus Walleij
On Mon, Jul 7, 2025 at 5:39 PM Paul Kocialkowski <paulk@sys-base.io> wrote:
>
> Hi Chen-Yu,
>
> Le Sun 06 Jul 25, 23:04, Chen-Yu Tsai a écrit :
> > On Sun, Jul 6, 2025 at 8:00 AM Paul Kocialkowski <paulk@sys-base.io> wrote:
> > >
> > > Hi Andre,
> > >
> > > Le Sat 05 Jul 25, 15:38, Andre Przywara a écrit :
> > > > On Fri, 4 Jul 2025 23:35:35 +0100
> > > > Andre Przywara <andre.przywara@arm.com> wrote:
> > > >
> > > > Hi,
> > > >
> > > > > On Thu, 26 Jun 2025 10:09:19 +0200
> > > > > Paul Kocialkowski <paulk@sys-base.io> wrote:
> > > > >
> > > > > Hi Paul,
> > > > >
> > > > > > The Allwinner A100/A133 only has a single emac instance, which is
> > > > > > referred to as "emac" everywhere. Fix the pin names to drop the
> > > > > > trailing "0" that has no reason to be.
> > > > >
> > > > > Sorry, but this is wrong. There *is* a second EMAC on the A133 die: it's
> > > > > indeed not mentioned in the manual, but you can probe its MMIO
> > > > > registers (@0x5030000), and there is a second syscon register
> > > > > (@0x03000034). It's mentioned in several BSP code places ([1]).
> > > > > It seem like no suitable pins are connected on the A133
> > > > > package, but that should not affect the A100 .dtsi (we use a similar
> > > > > approach for the H616 and A523).
> > > > >
> > > > > So I think we should keep the emac0 name.
> > > >
> > > > just thinking that it's even worse: this changes the DT visible pinctrl
> > > > function name, so it's a DT ABI change. With the "emac0" function name,
> > > > Ethernet would work with stable kernels already (as everything is
> > > > compatible, it's just about DT changes). But with this change, pinctrl
> > > > drivers in older kernels would not match.
> > >
> > > Given that the port is still very early and experimental and has very few users
> > > and no field deployment so I don't really think it would have annoyed anybody in
> > > practice. But yes in principle you are right, while the header renames keep the
> > > same value, the string names are used to match the device-tree definitions and
> > > this constitues ABI that needs to remain stable.
> > >
> > > > So I would very much like to see this patch moved out. Is it just in
> > > > LinusW's tree so far? I don't see it in -next yet.
> > >
> > > I don't think the patches were accepted for over a week so we can probably
> > > still act. I will send reverts, unless maintainers want to manually remove
> > > these commits?
> >
> > I can drop the dts patches from the sunxi tree. Linus might be able to
> > drop the pinctrl patch.
> >
> > You definitely need to send a revert for the DT binding patch that is
> > already in net-next.
>
> Should this really affect the bindings though?
>
> From what Andre reported, both EMAC0 and EMAC1 should be the same block so it
> doesn't seem particularly necessary to have a different compatible.
>
> Looking at Allwiner's BSP code for the A133[0], I don't see any difference
> between the two. While there's device_type property in Allwinner's dt, it's
> apparently not used by the driver[1].
>
> So I think we're still fine with a single compatible (without the controller
> index in it).
The block is the same, but the integration is slightly different, as
the register for the RGMII clock delays and other stuff is at a different
offset in the system controller. The BSP handles this by directly
including the register in the "reg" property.
So yes, you do need a separate compatible string, if only to deal with
the slight difference in the integration layer.
ChenYu
> [0]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi#L2016
> [1]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/drivers/net/ethernet/allwinner/sunxi-gmac.c
>
> All the best,
>
> Paul
>
> >
> > ChenYu
> >
> >
> > > Cheers,
> > >
> > > Paul
> > >
> > > > Cheers,
> > > > Andre.
> > > >
> > > > > [1]
> > > > > https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
> > > > >
> > > > >
> > > > > >
> > > > > > Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> > > > > > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> > > > > > ---
> > > > > > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> > > > > > 1 file changed, 16 insertions(+), 16 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > index b97de80ae2f3..95b764ee1c0d 100644
> > > > > > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> > > > > > SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> > > > > > SUNXI_FUNCTION(0x4, "ledc"),
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> > > > > > SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> > > > > > SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> > > > > > SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> > > > > > SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > >
> > > > >
> > > >
> > >
> > > --
> > > Paul Kocialkowski,
> > >
> > > Independent contractor - sys-base - https://www.sys-base.io/
> > > Free software developer - https://www.paulk.fr/
> > >
> > > Expert in multimedia, graphics and embedded hardware support with Linux.
>
> --
> Paul Kocialkowski,
>
> Independent contractor - sys-base - https://www.sys-base.io/
> Free software developer - https://www.paulk.fr/
>
> Expert in multimedia, graphics and embedded hardware support with Linux.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-07-07 9:52 ` Chen-Yu Tsai
@ 2025-07-07 10:13 ` Paul Kocialkowski
2025-07-07 10:22 ` Chen-Yu Tsai
0 siblings, 1 reply; 30+ messages in thread
From: Paul Kocialkowski @ 2025-07-07 10:13 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Andre Przywara, netdev, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec, Samuel Holland,
Linus Walleij
[-- Attachment #1: Type: text/plain, Size: 15511 bytes --]
Hi,
Le Mon 07 Jul 25, 17:52, Chen-Yu Tsai a écrit :
> On Mon, Jul 7, 2025 at 5:39 PM Paul Kocialkowski <paulk@sys-base.io> wrote:
> >
> > Hi Chen-Yu,
> >
> > Le Sun 06 Jul 25, 23:04, Chen-Yu Tsai a écrit :
> > > On Sun, Jul 6, 2025 at 8:00 AM Paul Kocialkowski <paulk@sys-base.io> wrote:
> > > >
> > > > Hi Andre,
> > > >
> > > > Le Sat 05 Jul 25, 15:38, Andre Przywara a écrit :
> > > > > On Fri, 4 Jul 2025 23:35:35 +0100
> > > > > Andre Przywara <andre.przywara@arm.com> wrote:
> > > > >
> > > > > Hi,
> > > > >
> > > > > > On Thu, 26 Jun 2025 10:09:19 +0200
> > > > > > Paul Kocialkowski <paulk@sys-base.io> wrote:
> > > > > >
> > > > > > Hi Paul,
> > > > > >
> > > > > > > The Allwinner A100/A133 only has a single emac instance, which is
> > > > > > > referred to as "emac" everywhere. Fix the pin names to drop the
> > > > > > > trailing "0" that has no reason to be.
> > > > > >
> > > > > > Sorry, but this is wrong. There *is* a second EMAC on the A133 die: it's
> > > > > > indeed not mentioned in the manual, but you can probe its MMIO
> > > > > > registers (@0x5030000), and there is a second syscon register
> > > > > > (@0x03000034). It's mentioned in several BSP code places ([1]).
> > > > > > It seem like no suitable pins are connected on the A133
> > > > > > package, but that should not affect the A100 .dtsi (we use a similar
> > > > > > approach for the H616 and A523).
> > > > > >
> > > > > > So I think we should keep the emac0 name.
> > > > >
> > > > > just thinking that it's even worse: this changes the DT visible pinctrl
> > > > > function name, so it's a DT ABI change. With the "emac0" function name,
> > > > > Ethernet would work with stable kernels already (as everything is
> > > > > compatible, it's just about DT changes). But with this change, pinctrl
> > > > > drivers in older kernels would not match.
> > > >
> > > > Given that the port is still very early and experimental and has very few users
> > > > and no field deployment so I don't really think it would have annoyed anybody in
> > > > practice. But yes in principle you are right, while the header renames keep the
> > > > same value, the string names are used to match the device-tree definitions and
> > > > this constitues ABI that needs to remain stable.
> > > >
> > > > > So I would very much like to see this patch moved out. Is it just in
> > > > > LinusW's tree so far? I don't see it in -next yet.
> > > >
> > > > I don't think the patches were accepted for over a week so we can probably
> > > > still act. I will send reverts, unless maintainers want to manually remove
> > > > these commits?
> > >
> > > I can drop the dts patches from the sunxi tree. Linus might be able to
> > > drop the pinctrl patch.
> > >
> > > You definitely need to send a revert for the DT binding patch that is
> > > already in net-next.
> >
> > Should this really affect the bindings though?
> >
> > From what Andre reported, both EMAC0 and EMAC1 should be the same block so it
> > doesn't seem particularly necessary to have a different compatible.
> >
> > Looking at Allwiner's BSP code for the A133[0], I don't see any difference
> > between the two. While there's device_type property in Allwinner's dt, it's
> > apparently not used by the driver[1].
> >
> > So I think we're still fine with a single compatible (without the controller
> > index in it).
>
> The block is the same, but the integration is slightly different, as
> the register for the RGMII clock delays and other stuff is at a different
> offset in the system controller. The BSP handles this by directly
> including the register in the "reg" property.
Ah I see, I forgot about the syscon register. However it doesn't seem like a
very good approach to have a different compatible to express the idea that an
external resource is different. Just like we do for clocks, resets and other
things, we should probably find a way to express the offset via some dedicated
property instead of spinning a different compatible each time it changes.
> So yes, you do need a separate compatible string, if only to deal with
> the slight difference in the integration layer.
So maybe an additional allwinner,syscon-offset property or a new
allwinner,syscon that takes the syscon phandle first and the offset second?
It seems that various other platforms are doing similar things (e.g.
ti,syscon-pcie-mode).
Thanks
Paul
>
> ChenYu
>
> > [0]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi#L2016
> > [1]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/drivers/net/ethernet/allwinner/sunxi-gmac.c
> >
> > All the best,
> >
> > Paul
> >
> > >
> > > ChenYu
> > >
> > >
> > > > Cheers,
> > > >
> > > > Paul
> > > >
> > > > > Cheers,
> > > > > Andre.
> > > > >
> > > > > > [1]
> > > > > > https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
> > > > > >
> > > > > >
> > > > > > >
> > > > > > > Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> > > > > > > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> > > > > > > ---
> > > > > > > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> > > > > > > 1 file changed, 16 insertions(+), 16 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > index b97de80ae2f3..95b764ee1c0d 100644
> > > > > > > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> > > > > > > SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> > > > > > > SUNXI_FUNCTION(0x4, "ledc"),
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> > > > > > > SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> > > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> > > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> > > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> > > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > >
> > > > > >
> > > > >
> > > >
> > > > --
> > > > Paul Kocialkowski,
> > > >
> > > > Independent contractor - sys-base - https://www.sys-base.io/
> > > > Free software developer - https://www.paulk.fr/
> > > >
> > > > Expert in multimedia, graphics and embedded hardware support with Linux.
> >
> > --
> > Paul Kocialkowski,
> >
> > Independent contractor - sys-base - https://www.sys-base.io/
> > Free software developer - https://www.paulk.fr/
> >
> > Expert in multimedia, graphics and embedded hardware support with Linux.
--
Paul Kocialkowski,
Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/
Expert in multimedia, graphics and embedded hardware support with Linux.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-07-07 10:13 ` Paul Kocialkowski
@ 2025-07-07 10:22 ` Chen-Yu Tsai
2025-07-07 10:40 ` Paul Kocialkowski
0 siblings, 1 reply; 30+ messages in thread
From: Chen-Yu Tsai @ 2025-07-07 10:22 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: Andre Przywara, netdev, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec, Samuel Holland,
Linus Walleij
On Mon, Jul 7, 2025 at 6:13 PM Paul Kocialkowski <paulk@sys-base.io> wrote:
>
> Hi,
>
> Le Mon 07 Jul 25, 17:52, Chen-Yu Tsai a écrit :
> > On Mon, Jul 7, 2025 at 5:39 PM Paul Kocialkowski <paulk@sys-base.io> wrote:
> > >
> > > Hi Chen-Yu,
> > >
> > > Le Sun 06 Jul 25, 23:04, Chen-Yu Tsai a écrit :
> > > > On Sun, Jul 6, 2025 at 8:00 AM Paul Kocialkowski <paulk@sys-base.io> wrote:
> > > > >
> > > > > Hi Andre,
> > > > >
> > > > > Le Sat 05 Jul 25, 15:38, Andre Przywara a écrit :
> > > > > > On Fri, 4 Jul 2025 23:35:35 +0100
> > > > > > Andre Przywara <andre.przywara@arm.com> wrote:
> > > > > >
> > > > > > Hi,
> > > > > >
> > > > > > > On Thu, 26 Jun 2025 10:09:19 +0200
> > > > > > > Paul Kocialkowski <paulk@sys-base.io> wrote:
> > > > > > >
> > > > > > > Hi Paul,
> > > > > > >
> > > > > > > > The Allwinner A100/A133 only has a single emac instance, which is
> > > > > > > > referred to as "emac" everywhere. Fix the pin names to drop the
> > > > > > > > trailing "0" that has no reason to be.
> > > > > > >
> > > > > > > Sorry, but this is wrong. There *is* a second EMAC on the A133 die: it's
> > > > > > > indeed not mentioned in the manual, but you can probe its MMIO
> > > > > > > registers (@0x5030000), and there is a second syscon register
> > > > > > > (@0x03000034). It's mentioned in several BSP code places ([1]).
> > > > > > > It seem like no suitable pins are connected on the A133
> > > > > > > package, but that should not affect the A100 .dtsi (we use a similar
> > > > > > > approach for the H616 and A523).
> > > > > > >
> > > > > > > So I think we should keep the emac0 name.
> > > > > >
> > > > > > just thinking that it's even worse: this changes the DT visible pinctrl
> > > > > > function name, so it's a DT ABI change. With the "emac0" function name,
> > > > > > Ethernet would work with stable kernels already (as everything is
> > > > > > compatible, it's just about DT changes). But with this change, pinctrl
> > > > > > drivers in older kernels would not match.
> > > > >
> > > > > Given that the port is still very early and experimental and has very few users
> > > > > and no field deployment so I don't really think it would have annoyed anybody in
> > > > > practice. But yes in principle you are right, while the header renames keep the
> > > > > same value, the string names are used to match the device-tree definitions and
> > > > > this constitues ABI that needs to remain stable.
> > > > >
> > > > > > So I would very much like to see this patch moved out. Is it just in
> > > > > > LinusW's tree so far? I don't see it in -next yet.
> > > > >
> > > > > I don't think the patches were accepted for over a week so we can probably
> > > > > still act. I will send reverts, unless maintainers want to manually remove
> > > > > these commits?
> > > >
> > > > I can drop the dts patches from the sunxi tree. Linus might be able to
> > > > drop the pinctrl patch.
> > > >
> > > > You definitely need to send a revert for the DT binding patch that is
> > > > already in net-next.
> > >
> > > Should this really affect the bindings though?
> > >
> > > From what Andre reported, both EMAC0 and EMAC1 should be the same block so it
> > > doesn't seem particularly necessary to have a different compatible.
> > >
> > > Looking at Allwiner's BSP code for the A133[0], I don't see any difference
> > > between the two. While there's device_type property in Allwinner's dt, it's
> > > apparently not used by the driver[1].
> > >
> > > So I think we're still fine with a single compatible (without the controller
> > > index in it).
> >
> > The block is the same, but the integration is slightly different, as
> > the register for the RGMII clock delays and other stuff is at a different
> > offset in the system controller. The BSP handles this by directly
> > including the register in the "reg" property.
>
> Ah I see, I forgot about the syscon register. However it doesn't seem like a
> very good approach to have a different compatible to express the idea that an
> external resource is different. Just like we do for clocks, resets and other
> things, we should probably find a way to express the offset via some dedicated
> property instead of spinning a different compatible each time it changes.
>
> > So yes, you do need a separate compatible string, if only to deal with
> > the slight difference in the integration layer.
>
> So maybe an additional allwinner,syscon-offset property or a new
If you can get that accepted, I think that works?
> allwinner,syscon that takes the syscon phandle first and the offset second?
I would prefer to avoid any changes to the syscon reference that would
require more custom code. I only just recently found that we could use
the standard syscon code with the provider registering the syscon. We
could drop the of_parse_phandle() + find device + dev_get_regmap() bits.
This is partially covered in my GMAC200 series.
ChenYu
> It seems that various other platforms are doing similar things (e.g.
> ti,syscon-pcie-mode).
>
> Thanks
>
> Paul
>
> >
> > ChenYu
> >
> > > [0]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi#L2016
> > > [1]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/drivers/net/ethernet/allwinner/sunxi-gmac.c
> > >
> > > All the best,
> > >
> > > Paul
> > >
> > > >
> > > > ChenYu
> > > >
> > > >
> > > > > Cheers,
> > > > >
> > > > > Paul
> > > > >
> > > > > > Cheers,
> > > > > > Andre.
> > > > > >
> > > > > > > [1]
> > > > > > > https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
> > > > > > >
> > > > > > >
> > > > > > > >
> > > > > > > > Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> > > > > > > > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> > > > > > > > ---
> > > > > > > > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> > > > > > > > 1 file changed, 16 insertions(+), 16 deletions(-)
> > > > > > > >
> > > > > > > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > > index b97de80ae2f3..95b764ee1c0d 100644
> > > > > > > > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > > @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> > > > > > > > SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> > > > > > > > SUNXI_FUNCTION(0x4, "ledc"),
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> > > > > > > > SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> > > > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> > > > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> > > > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> > > > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> > > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> > > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> > > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> > > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> > > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > >
> > > > > > >
> > > > > >
> > > > >
> > > > > --
> > > > > Paul Kocialkowski,
> > > > >
> > > > > Independent contractor - sys-base - https://www.sys-base.io/
> > > > > Free software developer - https://www.paulk.fr/
> > > > >
> > > > > Expert in multimedia, graphics and embedded hardware support with Linux.
> > >
> > > --
> > > Paul Kocialkowski,
> > >
> > > Independent contractor - sys-base - https://www.sys-base.io/
> > > Free software developer - https://www.paulk.fr/
> > >
> > > Expert in multimedia, graphics and embedded hardware support with Linux.
>
> --
> Paul Kocialkowski,
>
> Independent contractor - sys-base - https://www.sys-base.io/
> Free software developer - https://www.paulk.fr/
>
> Expert in multimedia, graphics and embedded hardware support with Linux.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-07-07 10:22 ` Chen-Yu Tsai
@ 2025-07-07 10:40 ` Paul Kocialkowski
2025-07-07 12:38 ` Andre Przywara
0 siblings, 1 reply; 30+ messages in thread
From: Paul Kocialkowski @ 2025-07-07 10:40 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Andre Przywara, netdev, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec, Samuel Holland,
Linus Walleij
[-- Attachment #1: Type: text/plain, Size: 13838 bytes --]
Chen-Yu,
> > > The block is the same, but the integration is slightly different, as
> > > the register for the RGMII clock delays and other stuff is at a different
> > > offset in the system controller. The BSP handles this by directly
> > > including the register in the "reg" property.
> >
> > Ah I see, I forgot about the syscon register. However it doesn't seem like a
> > very good approach to have a different compatible to express the idea that an
> > external resource is different. Just like we do for clocks, resets and other
> > things, we should probably find a way to express the offset via some dedicated
> > property instead of spinning a different compatible each time it changes.
> >
> > > So yes, you do need a separate compatible string, if only to deal with
> > > the slight difference in the integration layer.
> >
> > So maybe an additional allwinner,syscon-offset property or a new
>
> If you can get that accepted, I think that works?
>
> > allwinner,syscon that takes the syscon phandle first and the offset second?
>
> I would prefer to avoid any changes to the syscon reference that would
> require more custom code. I only just recently found that we could use
> the standard syscon code with the provider registering the syscon. We
> could drop the of_parse_phandle() + find device + dev_get_regmap() bits.
> This is partially covered in my GMAC200 series.
There is already syscon_regmap_lookup_by_phandle_args which supports generic
extra arguments to a syscon node. It just requires a custom syscon property.
I personally find this cleaner than adding a property just for the offset.
Paul
> ChenYu
>
> > It seems that various other platforms are doing similar things (e.g.
> > ti,syscon-pcie-mode).
> >
> > Thanks
> >
> > Paul
> >
> > >
> > > ChenYu
> > >
> > > > [0]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi#L2016
> > > > [1]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/drivers/net/ethernet/allwinner/sunxi-gmac.c
> > > >
> > > > All the best,
> > > >
> > > > Paul
> > > >
> > > > >
> > > > > ChenYu
> > > > >
> > > > >
> > > > > > Cheers,
> > > > > >
> > > > > > Paul
> > > > > >
> > > > > > > Cheers,
> > > > > > > Andre.
> > > > > > >
> > > > > > > > [1]
> > > > > > > > https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
> > > > > > > >
> > > > > > > >
> > > > > > > > >
> > > > > > > > > Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> > > > > > > > > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> > > > > > > > > ---
> > > > > > > > > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> > > > > > > > > 1 file changed, 16 insertions(+), 16 deletions(-)
> > > > > > > > >
> > > > > > > > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > > > index b97de80ae2f3..95b764ee1c0d 100644
> > > > > > > > > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > > > @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> > > > > > > > > SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> > > > > > > > > SUNXI_FUNCTION(0x4, "ledc"),
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> > > > > > > > > SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> > > > > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> > > > > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> > > > > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> > > > > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> > > > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > >
> > > > > > > >
> > > > > > >
> > > > > >
> > > > > > --
> > > > > > Paul Kocialkowski,
> > > > > >
> > > > > > Independent contractor - sys-base - https://www.sys-base.io/
> > > > > > Free software developer - https://www.paulk.fr/
> > > > > >
> > > > > > Expert in multimedia, graphics and embedded hardware support with Linux.
> > > >
> > > > --
> > > > Paul Kocialkowski,
> > > >
> > > > Independent contractor - sys-base - https://www.sys-base.io/
> > > > Free software developer - https://www.paulk.fr/
> > > >
> > > > Expert in multimedia, graphics and embedded hardware support with Linux.
> >
> > --
> > Paul Kocialkowski,
> >
> > Independent contractor - sys-base - https://www.sys-base.io/
> > Free software developer - https://www.paulk.fr/
> >
> > Expert in multimedia, graphics and embedded hardware support with Linux.
--
Paul Kocialkowski,
Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/
Expert in multimedia, graphics and embedded hardware support with Linux.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-07-07 10:40 ` Paul Kocialkowski
@ 2025-07-07 12:38 ` Andre Przywara
2025-07-07 13:19 ` Paul Kocialkowski
2025-07-07 15:27 ` Chen-Yu Tsai
0 siblings, 2 replies; 30+ messages in thread
From: Andre Przywara @ 2025-07-07 12:38 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: Chen-Yu Tsai, netdev, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec, Samuel Holland,
Linus Walleij
On Mon, 7 Jul 2025 12:40:46 +0200
Paul Kocialkowski <paulk@sys-base.io> wrote:
> Chen-Yu,
>
> > > > The block is the same, but the integration is slightly different, as
> > > > the register for the RGMII clock delays and other stuff is at a different
> > > > offset in the system controller. The BSP handles this by directly
> > > > including the register in the "reg" property.
> > >
> > > Ah I see, I forgot about the syscon register. However it doesn't seem like a
> > > very good approach to have a different compatible to express the idea that an
> > > external resource is different. Just like we do for clocks, resets and other
> > > things, we should probably find a way to express the offset via some dedicated
> > > property instead of spinning a different compatible each time it changes.
> > >
> > > > So yes, you do need a separate compatible string, if only to deal with
> > > > the slight difference in the integration layer.
> > >
> > > So maybe an additional allwinner,syscon-offset property or a new
> >
> > If you can get that accepted, I think that works?
> >
> > > allwinner,syscon that takes the syscon phandle first and the offset second?
> >
> > I would prefer to avoid any changes to the syscon reference that would
> > require more custom code. I only just recently found that we could use
> > the standard syscon code with the provider registering the syscon. We
> > could drop the of_parse_phandle() + find device + dev_get_regmap() bits.
> > This is partially covered in my GMAC200 series.
>
> There is already syscon_regmap_lookup_by_phandle_args which supports generic
> extra arguments to a syscon node. It just requires a custom syscon property.
>
> I personally find this cleaner than adding a property just for the offset.
Well, I proposed that already for the H616, where the second EMAC has the
same problem with the syscon at 0x34 instead of 0x30:
https://lore.kernel.org/linux-sunxi/20210615110636.23403-10-andre.przywara@arm.com/
I don't remember the details, but it got eventually dropped, partly
because the 2nd EMAC isn't supported yet due to missing AC200/AC300
support.
My plan was to let <&syscon> be the same as <&syscon 0>, which would
preserve compatibility. Though I am not sure the fallback compatible is
then correct, because it typically means that older driver can cope with
those devices, which isn't really the case here.
But we could postpone this issue as well for the A133, to the day when
there will be a device using this 2nd MAC.
Cheers,
Andre
>
> Paul
>
> > ChenYu
> >
> > > It seems that various other platforms are doing similar things (e.g.
> > > ti,syscon-pcie-mode).
> > >
> > > Thanks
> > >
> > > Paul
> > >
> > > >
> > > > ChenYu
> > > >
> > > > > [0]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi#L2016
> > > > > [1]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/drivers/net/ethernet/allwinner/sunxi-gmac.c
> > > > >
> > > > > All the best,
> > > > >
> > > > > Paul
> > > > >
> > > > > >
> > > > > > ChenYu
> > > > > >
> > > > > >
> > > > > > > Cheers,
> > > > > > >
> > > > > > > Paul
> > > > > > >
> > > > > > > > Cheers,
> > > > > > > > Andre.
> > > > > > > >
> > > > > > > > > [1]
> > > > > > > > > https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> > > > > > > > > > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> > > > > > > > > > ---
> > > > > > > > > > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> > > > > > > > > > 1 file changed, 16 insertions(+), 16 deletions(-)
> > > > > > > > > >
> > > > > > > > > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > > > > index b97de80ae2f3..95b764ee1c0d 100644
> > > > > > > > > > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > > > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > > > > @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> > > > > > > > > > SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> > > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> > > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> > > > > > > > > > SUNXI_FUNCTION(0x4, "ledc"),
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> > > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> > > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> > > > > > > > > > SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> > > > > > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> > > > > > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> > > > > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > >
> > > > > > > > >
> > > > > > > >
> > > > > > >
> > > > > > > --
> > > > > > > Paul Kocialkowski,
> > > > > > >
> > > > > > > Independent contractor - sys-base - https://www.sys-base.io/
> > > > > > > Free software developer - https://www.paulk.fr/
> > > > > > >
> > > > > > > Expert in multimedia, graphics and embedded hardware support with Linux.
> > > > >
> > > > > --
> > > > > Paul Kocialkowski,
> > > > >
> > > > > Independent contractor - sys-base - https://www.sys-base.io/
> > > > > Free software developer - https://www.paulk.fr/
> > > > >
> > > > > Expert in multimedia, graphics and embedded hardware support with Linux.
> > >
> > > --
> > > Paul Kocialkowski,
> > >
> > > Independent contractor - sys-base - https://www.sys-base.io/
> > > Free software developer - https://www.paulk.fr/
> > >
> > > Expert in multimedia, graphics and embedded hardware support with Linux.
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-07-07 12:38 ` Andre Przywara
@ 2025-07-07 13:19 ` Paul Kocialkowski
2025-07-07 15:27 ` Chen-Yu Tsai
1 sibling, 0 replies; 30+ messages in thread
From: Paul Kocialkowski @ 2025-07-07 13:19 UTC (permalink / raw)
To: Andre Przywara
Cc: Chen-Yu Tsai, netdev, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec, Samuel Holland,
Linus Walleij
[-- Attachment #1: Type: text/plain, Size: 16399 bytes --]
Hi,
Le Mon 07 Jul 25, 13:38, Andre Przywara a écrit :
> On Mon, 7 Jul 2025 12:40:46 +0200
> Paul Kocialkowski <paulk@sys-base.io> wrote:
>
> > Chen-Yu,
> >
> > > > > The block is the same, but the integration is slightly different, as
> > > > > the register for the RGMII clock delays and other stuff is at a different
> > > > > offset in the system controller. The BSP handles this by directly
> > > > > including the register in the "reg" property.
> > > >
> > > > Ah I see, I forgot about the syscon register. However it doesn't seem like a
> > > > very good approach to have a different compatible to express the idea that an
> > > > external resource is different. Just like we do for clocks, resets and other
> > > > things, we should probably find a way to express the offset via some dedicated
> > > > property instead of spinning a different compatible each time it changes.
> > > >
> > > > > So yes, you do need a separate compatible string, if only to deal with
> > > > > the slight difference in the integration layer.
> > > >
> > > > So maybe an additional allwinner,syscon-offset property or a new
> > >
> > > If you can get that accepted, I think that works?
> > >
> > > > allwinner,syscon that takes the syscon phandle first and the offset second?
> > >
> > > I would prefer to avoid any changes to the syscon reference that would
> > > require more custom code. I only just recently found that we could use
> > > the standard syscon code with the provider registering the syscon. We
> > > could drop the of_parse_phandle() + find device + dev_get_regmap() bits.
> > > This is partially covered in my GMAC200 series.
> >
> > There is already syscon_regmap_lookup_by_phandle_args which supports generic
> > extra arguments to a syscon node. It just requires a custom syscon property.
> >
> > I personally find this cleaner than adding a property just for the offset.
>
> Well, I proposed that already for the H616, where the second EMAC has the
> same problem with the syscon at 0x34 instead of 0x30:
>
> https://lore.kernel.org/linux-sunxi/20210615110636.23403-10-andre.przywara@arm.com/
>
> I don't remember the details, but it got eventually dropped, partly
> because the 2nd EMAC isn't supported yet due to missing AC200/AC300
> support.
> My plan was to let <&syscon> be the same as <&syscon 0>, which would
> preserve compatibility.
Well the syscon property is already defined in the binding as a single phandle
so I'm not sure we could just extend it. It looks like other consumers that
require an extra argument typically have a vendor prefix.
> Though I am not sure the fallback compatible is
> then correct, because it typically means that older driver can cope with
> those devices, which isn't really the case here.
>
> But we could postpone this issue as well for the A133, to the day when
> there will be a device using this 2nd MAC.
Yes as long as this opens a way to support both EMACs with the same compatible
it sounds good to me. No need to implement this right now.
So with the sunxi device-tree patches out I think we're only looking at the
pinctrl tree. I can see the patches were pushed on the repo now, so I should
probably better send a revert at this point.
All the best,
Paul
> Cheers,
> Andre
>
>
> >
> > Paul
> >
> > > ChenYu
> > >
> > > > It seems that various other platforms are doing similar things (e.g.
> > > > ti,syscon-pcie-mode).
> > > >
> > > > Thanks
> > > >
> > > > Paul
> > > >
> > > > >
> > > > > ChenYu
> > > > >
> > > > > > [0]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi#L2016
> > > > > > [1]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/drivers/net/ethernet/allwinner/sunxi-gmac.c
> > > > > >
> > > > > > All the best,
> > > > > >
> > > > > > Paul
> > > > > >
> > > > > > >
> > > > > > > ChenYu
> > > > > > >
> > > > > > >
> > > > > > > > Cheers,
> > > > > > > >
> > > > > > > > Paul
> > > > > > > >
> > > > > > > > > Cheers,
> > > > > > > > > Andre.
> > > > > > > > >
> > > > > > > > > > [1]
> > > > > > > > > > https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > > Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> > > > > > > > > > > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> > > > > > > > > > > ---
> > > > > > > > > > > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> > > > > > > > > > > 1 file changed, 16 insertions(+), 16 deletions(-)
> > > > > > > > > > >
> > > > > > > > > > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > > > > > index b97de80ae2f3..95b764ee1c0d 100644
> > > > > > > > > > > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > > > > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > > > > > @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "ledc"),
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > >
> > > > > > > >
> > > > > > > > --
> > > > > > > > Paul Kocialkowski,
> > > > > > > >
> > > > > > > > Independent contractor - sys-base - https://www.sys-base.io/
> > > > > > > > Free software developer - https://www.paulk.fr/
> > > > > > > >
> > > > > > > > Expert in multimedia, graphics and embedded hardware support with Linux.
> > > > > >
> > > > > > --
> > > > > > Paul Kocialkowski,
> > > > > >
> > > > > > Independent contractor - sys-base - https://www.sys-base.io/
> > > > > > Free software developer - https://www.paulk.fr/
> > > > > >
> > > > > > Expert in multimedia, graphics and embedded hardware support with Linux.
> > > >
> > > > --
> > > > Paul Kocialkowski,
> > > >
> > > > Independent contractor - sys-base - https://www.sys-base.io/
> > > > Free software developer - https://www.paulk.fr/
> > > >
> > > > Expert in multimedia, graphics and embedded hardware support with Linux.
> >
>
--
Paul Kocialkowski,
Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/
Expert in multimedia, graphics and embedded hardware support with Linux.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-07-07 12:38 ` Andre Przywara
2025-07-07 13:19 ` Paul Kocialkowski
@ 2025-07-07 15:27 ` Chen-Yu Tsai
1 sibling, 0 replies; 30+ messages in thread
From: Chen-Yu Tsai @ 2025-07-07 15:27 UTC (permalink / raw)
To: Andre Przywara
Cc: Paul Kocialkowski, netdev, devicetree, linux-arm-kernel,
linux-sunxi, linux-kernel, linux-gpio, Andrew Lunn,
David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec,
Samuel Holland, Linus Walleij
On Mon, Jul 7, 2025 at 8:38 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> On Mon, 7 Jul 2025 12:40:46 +0200
> Paul Kocialkowski <paulk@sys-base.io> wrote:
>
> > Chen-Yu,
> >
> > > > > The block is the same, but the integration is slightly different, as
> > > > > the register for the RGMII clock delays and other stuff is at a different
> > > > > offset in the system controller. The BSP handles this by directly
> > > > > including the register in the "reg" property.
> > > >
> > > > Ah I see, I forgot about the syscon register. However it doesn't seem like a
> > > > very good approach to have a different compatible to express the idea that an
> > > > external resource is different. Just like we do for clocks, resets and other
> > > > things, we should probably find a way to express the offset via some dedicated
> > > > property instead of spinning a different compatible each time it changes.
> > > >
> > > > > So yes, you do need a separate compatible string, if only to deal with
> > > > > the slight difference in the integration layer.
> > > >
> > > > So maybe an additional allwinner,syscon-offset property or a new
> > >
> > > If you can get that accepted, I think that works?
> > >
> > > > allwinner,syscon that takes the syscon phandle first and the offset second?
> > >
> > > I would prefer to avoid any changes to the syscon reference that would
> > > require more custom code. I only just recently found that we could use
> > > the standard syscon code with the provider registering the syscon. We
> > > could drop the of_parse_phandle() + find device + dev_get_regmap() bits.
> > > This is partially covered in my GMAC200 series.
> >
> > There is already syscon_regmap_lookup_by_phandle_args which supports generic
> > extra arguments to a syscon node. It just requires a custom syscon property.
> >
> > I personally find this cleaner than adding a property just for the offset.
>
> Well, I proposed that already for the H616, where the second EMAC has the
> same problem with the syscon at 0x34 instead of 0x30:
>
> https://lore.kernel.org/linux-sunxi/20210615110636.23403-10-andre.przywara@arm.com/
Nice.
> I don't remember the details, but it got eventually dropped, partly
> because the 2nd EMAC isn't supported yet due to missing AC200/AC300
> support.
> My plan was to let <&syscon> be the same as <&syscon 0>, which would
> preserve compatibility. Though I am not sure the fallback compatible is
> then correct, because it typically means that older driver can cope with
> those devices, which isn't really the case here.
>
> But we could postpone this issue as well for the A133, to the day when
> there will be a device using this 2nd MAC.
I guess I could maybe use it for the GMAC200 as well? Then if the GMAC200
is used in future chips we don't have to add another compatible string to
the driver.
ChenYu
> Cheers,
> Andre
>
>
> >
> > Paul
> >
> > > ChenYu
> > >
> > > > It seems that various other platforms are doing similar things (e.g.
> > > > ti,syscon-pcie-mode).
> > > >
> > > > Thanks
> > > >
> > > > Paul
> > > >
> > > > >
> > > > > ChenYu
> > > > >
> > > > > > [0]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi#L2016
> > > > > > [1]: https://github.com/engSinteck/A133_Image/blob/main/longan/kernel/linux-4.9/drivers/net/ethernet/allwinner/sunxi-gmac.c
> > > > > >
> > > > > > All the best,
> > > > > >
> > > > > > Paul
> > > > > >
> > > > > > >
> > > > > > > ChenYu
> > > > > > >
> > > > > > >
> > > > > > > > Cheers,
> > > > > > > >
> > > > > > > > Paul
> > > > > > > >
> > > > > > > > > Cheers,
> > > > > > > > > Andre.
> > > > > > > > >
> > > > > > > > > > [1]
> > > > > > > > > > https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > > Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> > > > > > > > > > > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> > > > > > > > > > > ---
> > > > > > > > > > > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> > > > > > > > > > > 1 file changed, 16 insertions(+), 16 deletions(-)
> > > > > > > > > > >
> > > > > > > > > > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > > > > > index b97de80ae2f3..95b764ee1c0d 100644
> > > > > > > > > > > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > > > > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > > > > > > > > > > @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "ledc"),
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > SUNXI_FUNCTION(0x1, "gpio_out"),
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > > > @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > > > > > > > > > > SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> > > > > > > > > > > SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> > > > > > > > > > > SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> > > > > > > > > > > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> > > > > > > > > > > + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> > > > > > > > > > > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> > > > > > > > > > > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> > > > > > > > > > > SUNXI_FUNCTION(0x0, "gpio_in"),
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > >
> > > > > > > >
> > > > > > > > --
> > > > > > > > Paul Kocialkowski,
> > > > > > > >
> > > > > > > > Independent contractor - sys-base - https://www.sys-base.io/
> > > > > > > > Free software developer - https://www.paulk.fr/
> > > > > > > >
> > > > > > > > Expert in multimedia, graphics and embedded hardware support with Linux.
> > > > > >
> > > > > > --
> > > > > > Paul Kocialkowski,
> > > > > >
> > > > > > Independent contractor - sys-base - https://www.sys-base.io/
> > > > > > Free software developer - https://www.paulk.fr/
> > > > > >
> > > > > > Expert in multimedia, graphics and embedded hardware support with Linux.
> > > >
> > > > --
> > > > Paul Kocialkowski,
> > > >
> > > > Independent contractor - sys-base - https://www.sys-base.io/
> > > > Free software developer - https://www.paulk.fr/
> > > >
> > > > Expert in multimedia, graphics and embedded hardware support with Linux.
> >
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
2025-07-06 15:04 ` Chen-Yu Tsai
2025-07-07 3:07 ` Chen-Yu Tsai
2025-07-07 9:39 ` Paul Kocialkowski
@ 2025-07-11 18:13 ` Linus Walleij
2 siblings, 0 replies; 30+ messages in thread
From: Linus Walleij @ 2025-07-11 18:13 UTC (permalink / raw)
To: wens
Cc: Paul Kocialkowski, Andre Przywara, netdev, devicetree,
linux-arm-kernel, linux-sunxi, linux-kernel, linux-gpio,
Andrew Lunn, David S . Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jernej Skrabec, Samuel Holland
On Sun, Jul 6, 2025 at 5:04 PM Chen-Yu Tsai <wens@csie.org> wrote:
> On Sun, Jul 6, 2025 at 8:00 AM Paul Kocialkowski <paulk@sys-base.io> wrote:
> > > So I would very much like to see this patch moved out. Is it just in
> > > LinusW's tree so far? I don't see it in -next yet.
> >
> > I don't think the patches were accepted for over a week so we can probably
> > still act. I will send reverts, unless maintainers want to manually remove
> > these commits?
>
> I can drop the dts patches from the sunxi tree. Linus might be able to
> drop the pinctrl patch.
>
> You definitely need to send a revert for the DT binding patch that is
> already in net-next.
I dropped the patch from the pinctrl tree, no problem.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2025-07-11 18:13 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-06-26 8:09 [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support Paul Kocialkowski
2025-06-26 8:09 ` [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name Paul Kocialkowski
2025-06-28 4:39 ` Chen-Yu Tsai
2025-07-04 8:02 ` Linus Walleij
2025-07-04 22:35 ` Andre Przywara
2025-07-05 14:38 ` Andre Przywara
2025-07-06 0:00 ` Paul Kocialkowski
2025-07-06 15:04 ` Chen-Yu Tsai
2025-07-07 3:07 ` Chen-Yu Tsai
2025-07-07 9:40 ` Paul Kocialkowski
2025-07-07 9:39 ` Paul Kocialkowski
2025-07-07 9:52 ` Chen-Yu Tsai
2025-07-07 10:13 ` Paul Kocialkowski
2025-07-07 10:22 ` Chen-Yu Tsai
2025-07-07 10:40 ` Paul Kocialkowski
2025-07-07 12:38 ` Andre Przywara
2025-07-07 13:19 ` Paul Kocialkowski
2025-07-07 15:27 ` Chen-Yu Tsai
2025-07-11 18:13 ` Linus Walleij
2025-07-05 23:52 ` Paul Kocialkowski
2025-06-26 8:09 ` [PATCH 2/5] arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII Paul Kocialkowski
2025-07-04 22:45 ` Andre Przywara
2025-06-26 8:09 ` [PATCH 3/5] dt-bindings: net: sun8i-emac: Add A100 EMAC compatible Paul Kocialkowski
2025-06-27 21:21 ` Rob Herring (Arm)
2025-07-04 22:40 ` Andre Przywara
2025-06-26 8:09 ` [PATCH 4/5] arm64: dts: allwinner: a100: Add EMAC support Paul Kocialkowski
2025-07-04 23:32 ` Andre Przywara
2025-06-26 8:09 ` [PATCH 5/5] arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support Paul Kocialkowski
2025-06-27 22:40 ` [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support patchwork-bot+netdevbpf
2025-07-04 15:37 ` (subset) " Chen-Yu Tsai
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