From: Arnd Bergmann <arnd@arndb.de>
To: Sunil Kovvuri <sunil.kovvuri@gmail.com>
Cc: Networking <netdev@vger.kernel.org>,
David Miller <davem@davemloft.net>,
linux-soc@vger.kernel.org, gakula@marvell.com,
sgoutham@marvell.com
Subject: Re: [PATCH v8 10/15] octeontx2-af: Reconfig MSIX base with IOVA
Date: Tue, 9 Oct 2018 09:57:25 +0200 [thread overview]
Message-ID: <CAK8P3a01YPk6Bpn4o10za8pebAHA8sfXAEEBAidfgcvbWwzFpA@mail.gmail.com> (raw)
In-Reply-To: <CA+sq2CcnthcB5S=Wo5bN_40A7==_jOcxD+b7Y-rkU35-gxwuJA@mail.gmail.com>
On Tue, Oct 9, 2018 at 9:03 AM Sunil Kovvuri <sunil.kovvuri@gmail.com> wrote:
> On Mon, Oct 8, 2018 at 5:38 PM Arnd Bergmann <arnd@arndb.de> wrote:
> > On Sun, Oct 7, 2018 at 5:01 PM <sunil.kovvuri@gmail.com> wrote:
> >
> > >
> > > + /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence
> > > + * create a IOMMU mapping for the physcial address configured by
> > > + * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA.
> > > + */
> > > + cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
> > > + max_msix = cfg & 0xFFFFF;
> > > + phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE);
> > > + iova = dma_map_single(rvu->dev, (void *)phy_addr,
> > > + max_msix * PCI_MSIX_ENTRY_SIZE,
> > > + DMA_BIDIRECTIONAL);
> > > + if (dma_mapping_error(rvu->dev, iova))
> > > + return -ENOMEM;
> > > +
> > > + rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova);
> > > + rvu->msix_base_iova = iova;
> > > +
> >
> > I'm a bit puzzled by how this works. Does this rely on a specific iommu
> > driver implementation? Normally a physical address makes no sense to the
> > implementation backing dma_map_single() that tries to convert a
> > linear kernel virtual address into a physical address.
> >
> > Arnd
>
> I understand what you are pointing at, but we did test this.
> IOMMU on this silicon is standard ARM64 SMMUv3.
I didn't doubt that you get the right results, I just couldn't see how ;-)
> All dma_map_single does is virt_to_page and iommu_dma_map_page
> converts it back i.e page_to_phys.
> So the IOMMU driver gets the same physical address passed above and
> creates a iova translation mapping.
>
> For reference below is the captured debug info for the same
> =====
> [ 19.435968] rvu_setup_msix_resources: phy_addr 0x3200000 iova 0xfff80000
> [ 19.436967] rvu_setup_msix_resources: virt_to_page(phy_addr)
> 0xffff7fe00000c800 page_to_phys(page) 0x3200000
> offset_in_page(phy_addr) 0x00
> =====
I think if you enable CONFIG_DEBUG_VIRTUAL, the virt_to_page()
above should trigger a warning in
phys_addr_t __virt_to_phys(unsigned long x)
{
WARN(!__is_lm_address(x),
"virt_to_phys used for non-linear address: %pK (%pS)\n",
(void *)x,
(void *)x);
return __virt_to_phys_nodebug(x);
}
Can you verify that?
Arnd
next prev parent reply other threads:[~2018-10-09 15:13 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-07 14:59 [PATCH v8 00/15] octeontx2-af: Add RVU Admin Function driver sunil.kovvuri
2018-10-07 14:59 ` [PATCH v8 01/15] octeontx2-af: Add Marvell OcteonTX2 RVU AF driver sunil.kovvuri
2018-10-08 12:22 ` Arnd Bergmann
2018-10-08 13:50 ` Sunil Kovvuri
2018-10-08 14:29 ` Arnd Bergmann
2018-10-07 14:59 ` [PATCH v8 02/15] octeontx2-af: Reset all RVU blocks sunil.kovvuri
2018-10-08 12:16 ` Arnd Bergmann
2018-10-09 7:10 ` Sunil Kovvuri
2018-10-07 14:59 ` [PATCH v8 03/15] octeontx2-af: Gather RVU blocks HW info sunil.kovvuri
2018-10-07 14:59 ` [PATCH v8 04/15] octeontx2-af: Add mailbox support infra sunil.kovvuri
2018-10-07 14:59 ` [PATCH v8 05/15] octeontx2-af: Add mailbox IRQ and msg handlers sunil.kovvuri
2018-10-08 4:11 ` David Miller
2018-10-07 14:59 ` [PATCH v8 06/15] octeontx2-af: Convert mbox msg id check to a macro sunil.kovvuri
2018-10-07 14:59 ` [PATCH v8 07/15] octeontx2-af: Scan blocks for LFs provisioned to PF/VF sunil.kovvuri
2018-10-07 14:59 ` [PATCH v8 08/15] octeontx2-af: Add RVU block LF provisioning support sunil.kovvuri
2018-10-08 12:11 ` Arnd Bergmann
2018-10-08 13:59 ` Sunil Kovvuri
2018-10-08 14:29 ` Arnd Bergmann
2018-10-07 14:59 ` [PATCH v8 09/15] octeontx2-af: Configure block LF's MSIX vector offset sunil.kovvuri
2018-10-07 14:59 ` [PATCH v8 10/15] octeontx2-af: Reconfig MSIX base with IOVA sunil.kovvuri
2018-10-08 12:08 ` Arnd Bergmann
2018-10-09 7:02 ` Sunil Kovvuri
2018-10-09 7:57 ` Arnd Bergmann [this message]
2018-10-09 9:20 ` Sunil Kovvuri
2018-10-09 12:00 ` Arnd Bergmann
2018-10-10 7:35 ` Sunil Kovvuri
2018-10-10 7:58 ` Arnd Bergmann
2018-10-07 14:59 ` [PATCH v8 11/15] octeontx2-af: Add Marvell OcteonTX2 CGX driver sunil.kovvuri
2018-10-07 14:59 ` [PATCH v8 12/15] octeontx2-af: Set RVU PFs to CGX LMACs mapping sunil.kovvuri
2018-10-07 14:59 ` [PATCH v8 13/15] octeontx2-af: Add support for CGX link management sunil.kovvuri
2018-10-07 14:59 ` [PATCH v8 14/15] octeontx2-af: Register for CGX lmac events sunil.kovvuri
2018-10-07 14:59 ` [PATCH v8 15/15] MAINTAINERS: Add entry for Marvell OcteonTX2 Admin Function driver sunil.kovvuri
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