From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 973E428504D for ; Thu, 2 Apr 2026 16:34:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775147692; cv=none; b=r7nfUpmHsnVF2KnuJdy3n7dJ8UtJbyEWoEc8/CXVHtjBXFQLiGmv3aksGxu5hrHvGiYJ6H6oCOrlBiVErklLD/fbV5KlL4CSr4yfTUfYNgmE7QrQh1NdkkR76Ez2ZxxQSCqLq89OwEjkv8xqMaLJw8vttanzkwmrpoZiah9+/MY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775147692; c=relaxed/simple; bh=3Dcbl0sj4+9NeJxnCcujmPHaFbsKV05jy1v8rfZV1zY=; h=Mime-Version:Content-Type:Date:Message-Id:To:From:Subject:Cc: References:In-Reply-To; b=BUOeH/XOFpG/OgWXCWQqXmE/11UN3JPsT0XqYzkfgU+MpjeMZFjQpiI7btAOlUu5Py8OfIwzjRjqXZIraAO04FXZIyFm504DKQMDHCBZem73f/ub2M3XdZLDJdTG7Q7khCRvPSmvh6haDN+mPU3Q0iQo0OOIltlTBcZvt2KdpxM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=n5UtK6Vj; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="n5UtK6Vj" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 2306D4E428BE; Thu, 2 Apr 2026 16:34:49 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id CC6A7602CD; Thu, 2 Apr 2026 16:34:48 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 1DAC910450283; Thu, 2 Apr 2026 18:34:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1775147687; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=vRWf3P80HFSecf7GD9AyzyNoy9HZEiwxJGyXlkzAnmo=; b=n5UtK6VjMPBVKk4cKC2cpxlUJtJdwXjjT1xtDPZbVdRuIiQEVyfnA7PlBOxLbKujIOUCQM 38U7wkRr7x1U47wPl2NYgtivVXa3r7NpGexYJrfGpi/mhvRXCloeMkgc4zgssTveUa+Q6S rlcpoxUeWVfCUntgqaLYqMLF+2poVBhyX4IOpxehtgknc0bQ8EFB+f2UaXVsz2tAYa+vfU 6lOXIImOrgKyrQ42A7Qoegj2BADk1LuEXQqP/wk/9PTS2OWVrMuxeM9hg4dTTr3YIJ8d1D onFICF46xFG/9Wh6wFCYbHcbFKZbW141HZ6qhicDjL56sXxLZ1ez6LuSQjRzvA== Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 02 Apr 2026 18:34:43 +0200 Message-Id: To: "Maxime Chevallier" , =?utf-8?q?Th=C3=A9o_Lebrun?= , "Nicolas Ferre" , "Claudiu Beznea" , "Andrew Lunn" , "David S. Miller" , "Eric Dumazet" , "Jakub Kicinski" , "Paolo Abeni" , "Richard Cochran" , "Russell King" From: =?utf-8?q?Th=C3=A9o_Lebrun?= Subject: Re: [PATCH net-next 10/11] net: macb: use context swapping in .set_ringparam() Cc: "Paolo Valerio" , "Conor Dooley" , "Nicolai Buchwitz" , "Vladimir Kondratiev" , "Gregory CLEMENT" , =?utf-8?q?Beno=C3=AEt_Monin?= , "Tawfik Bayouk" , "Thomas Petazzoni" , , X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260401-macb-context-v1-0-9590c5ab7272@bootlin.com> <20260401-macb-context-v1-10-9590c5ab7272@bootlin.com> In-Reply-To: X-Last-TLS-Session-Version: TLSv1.3 On Wed Apr 1, 2026 at 10:17 PM CEST, Maxime Chevallier wrote: > On 01/04/2026 18:39, Th=C3=A9o Lebrun wrote: >> ethtool_ops.set_ringparam() is implemented using the primitive close / >> update ring size / reopen sequence. Under memory pressure this does not >> fly: we free our buffers at close and cannot reallocate new ones at >> open. Also, it triggers a slow PHY reinit. >>=20 >> Instead, exploit the new context mechanism and improve our sequence to: >> - allocate a new context (including buffers) first >> - if it fails, early return without any impact to the interface >> - stop interface >> - update global state (bp, netdev, etc) >> - pass buffer pointers to the hardware >> - start interface >> - free old context. >>=20 >> The HW disable sequence is inspired by macb_reset_hw() but avoids >> (1) setting NCR bit CLRSTAT and (2) clearing register PBUFRXCUT. >>=20 >> The HW re-enable sequence is inspired by macb_mac_link_up(), skipping >> over register writes which would be redundant (because values have not >> changed). >>=20 >> The generic context swapping parts are isolated into helper functions >> macb_context_swap_start|end(), reusable by other operations (change_mtu, >> set_channels, etc). >>=20 >> Signed-off-by: Th=C3=A9o Lebrun >> --- >> drivers/net/ethernet/cadence/macb_main.c | 89 +++++++++++++++++++++++++= ++++--- >> 1 file changed, 82 insertions(+), 7 deletions(-) >>=20 >> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethe= rnet/cadence/macb_main.c >> index 42b19b969f3e..543356554c11 100644 >> --- a/drivers/net/ethernet/cadence/macb_main.c >> +++ b/drivers/net/ethernet/cadence/macb_main.c >> @@ -2905,6 +2905,76 @@ static struct macb_context *macb_context_alloc(st= ruct macb *bp, >> return ctx; >> } >> =20 >> +static void macb_context_swap_start(struct macb *bp) >> +{ >> + struct macb_queue *queue; >> + unsigned int q; >> + u32 ctrl; >> + >> + /* Disable software Tx, disable HW Tx/Rx and disable NAPI. */ >> + >> + netif_tx_disable(bp->netdev); >> + >> + ctrl =3D macb_readl(bp, NCR); >> + macb_writel(bp, NCR, ctrl & ~(MACB_BIT(RE) | MACB_BIT(TE))); >> + >> + macb_writel(bp, TSR, -1); >> + macb_writel(bp, RSR, -1); >> + >> + for (q =3D 0, queue =3D bp->queues; q < bp->num_queues; ++q, ++queue) = { >> + queue_writel(queue, IDR, -1); >> + queue_readl(queue, ISR); >> + if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) >> + queue_writel(queue, ISR, -1); >> + } > > These registers appear to be protected by bp->lock, any chance that this > may race with an interrupt in the middle of them being configured here ? The topic is complex! I dug deep this afternoon and replied to the neighbour thread by Nicolai. It might be of interest to you. https://lore.kernel.org/netdev/90f843aa3940bdbabadddce27314c1f1@tipi-net.de= / (will appear as a child to this email, it hasn't been indexed yet) Thanks Maxime, -- Th=C3=A9o Lebrun, Bootlin Embedded Linux and Kernel engineering https://bootlin.com