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[144.178.202.142]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bf051d82a31sm831571366b.19.2026.06.08.00.32.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jun 2026 00:32:55 -0700 (PDT) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 08 Jun 2026 09:32:54 +0200 Message-Id: Cc: "Ajit Pandey" , "Imran Shaik" , "Jagadeesh Kona" , , , , , , Subject: Re: [PATCH 5/5] arm64: dts: qcom: Add GP M/N clock controller node for SA8775P and QCS8300 From: "Luca Weiss" To: "Taniya Das" , "Bjorn Andersson" , "Michael Turquette" , "Stephen Boyd" , "Brian Masney" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Linus Walleij" , "Richard Cochran" , "Konrad Dybcio" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260602-pdm_clk_gp_mnd_v1-v1-0-1522662b6c53@oss.qualcomm.com> <20260602-pdm_clk_gp_mnd_v1-v1-5-1522662b6c53@oss.qualcomm.com> In-Reply-To: <20260602-pdm_clk_gp_mnd_v1-v1-5-1522662b6c53@oss.qualcomm.com> Hi Taniya, On Tue Jun 2, 2026 at 5:21 PM CEST, Taniya Das wrote: > Add the GP M/N divider clock controller node at 0x088d3000 to the > SA8775P (kodiak, lemans) and QCS8300 (monaco) SoC device trees. > > The node uses the qcom,clk-gp-mnd compatible, is clocked by the PDM > XO4 and AHB clocks from GCC, and exposes a single clock output > (gp_mn_clk) on the dedicated gp_mn pin mux function. The XO4 clock > is pre-assigned to 4.8 MHz (XO/4). > > Signed-off-by: Taniya Das > --- > arch/arm64/boot/dts/qcom/kodiak.dtsi | 14 ++++++++++++++ > arch/arm64/boot/dts/qcom/lemans.dtsi | 14 ++++++++++++++ > arch/arm64/boot/dts/qcom/monaco.dtsi | 14 ++++++++++++++ > 3 files changed, 42 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/q= com/kodiak.dtsi > index 1ff9e1598d00429c03b2bcae41fa370ab2c892bd..cbc13ac37f8aeb0b1071ad060= 9ec11e829d2c798 100644 > --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi > +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi > @@ -4412,6 +4412,20 @@ usb2_role_switch: endpoint { > }; > }; > =20 > + gp_mn: clock-controller@88d3000 { > + compatible =3D "qcom,clk-gp-mnd"; > + reg =3D <0x0 0x088d3000 0x0 0xc>; > + clocks =3D <&gcc GCC_PDM_XO4_CLK>, > + <&gcc GCC_PDM_AHB_CLK>; > + clock-names =3D "pdm_clk", "ahb_clk"; > + clock-output-names =3D "gp_mn_clk"; > + #clock-cells =3D <0>; > + pinctrl-names =3D "active"; > + pinctrl-0 =3D <&gp_mn_active>; > + assigned-clocks =3D <&gcc GCC_PDM_XO4_CLK>; > + assigned-clock-rates =3D <4800000>; > + }; Am I missing something, or would this just configure gpio60 for all boards for this clock controller output? On QCM6490 Fairphone 5 this pin is connected to FP_3P3_EN, so it's definitely not unused. Maybe disable them by default and let the board enable it, if it wants to make use of this clock? Regards Luca > + > qspi: spi@88dc000 { > compatible =3D "qcom,sc7280-qspi", "qcom,qspi-v1"; > reg =3D <0 0x088dc000 0 0x1000>; > diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/q= com/lemans.dtsi > index 19f8cf4e15482947f6049188050c370340afaead..d192f92a896bb13017abdf820= 62e8305aab3e5d5 100644 > --- a/arch/arm64/boot/dts/qcom/lemans.dtsi > +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi > @@ -4353,6 +4353,20 @@ opp-384000000 { > }; > }; > =20 > + gp_mn: clock-controller@88d3000 { > + compatible =3D "qcom,clk-gp-mnd"; > + reg =3D <0x0 0x088d3000 0x0 0xc>; > + clocks =3D <&gcc GCC_PDM_XO4_CLK>, > + <&gcc GCC_PDM_AHB_CLK>; > + clock-names =3D "pdm_clk", "ahb_clk"; > + clock-output-names =3D "gp_mn_clk"; > + #clock-cells =3D <0>; > + pinctrl-names =3D "active"; > + pinctrl-0 =3D <&gp_mn_active>; > + assigned-clocks =3D <&gcc GCC_PDM_XO4_CLK>; > + assigned-clock-rates =3D <4800000>; > + }; > + > usb_0_hsphy: phy@88e4000 { > compatible =3D "qcom,sa8775p-usb-hs-phy", > "qcom,usb-snps-hs-5nm-phy"; > diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/q= com/monaco.dtsi > index ebe5889daa5300efa7857314e9170d7d2fc33ef7..f6c5ec38c7491b7a16ebfb853= f8af88bdf1f0db3 100644 > --- a/arch/arm64/boot/dts/qcom/monaco.dtsi > +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi > @@ -4867,6 +4867,20 @@ opp-384000000 { > }; > }; > =20 > + gp_mn: clock-controller@88d3000 { > + compatible =3D "qcom,clk-gp-mnd"; > + reg =3D <0x0 0x088d3000 0x0 0xc>; > + clocks =3D <&gcc GCC_PDM_XO4_CLK>, > + <&gcc GCC_PDM_AHB_CLK>; > + clock-names =3D "pdm_clk", "ahb_clk"; > + clock-output-names =3D "gp_mn_clk"; > + #clock-cells =3D <0>; > + pinctrl-names =3D "active"; > + pinctrl-0 =3D <&gp_mn_active>; > + assigned-clocks =3D <&gcc GCC_PDM_XO4_CLK>; > + assigned-clock-rates =3D <4800000>; > + }; > + > usb_1_hsphy: phy@8904000 { > compatible =3D "qcom,qcs8300-usb-hs-phy", > "qcom,usb-snps-hs-7nm-phy";