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[144.178.202.142]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bf0522834dbsm815190666b.27.2026.06.08.00.33.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jun 2026 00:33:55 -0700 (PDT) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 08 Jun 2026 09:33:55 +0200 Message-Id: Cc: "Ajit Pandey" , "Imran Shaik" , "Jagadeesh Kona" , , , , , , Subject: Re: [PATCH 5/5] arm64: dts: qcom: Add GP M/N clock controller node for SA8775P and QCS8300 From: "Luca Weiss" To: "Taniya Das" , "Bjorn Andersson" , "Michael Turquette" , "Stephen Boyd" , "Brian Masney" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Linus Walleij" , "Richard Cochran" , "Konrad Dybcio" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260602-pdm_clk_gp_mnd_v1-v1-0-1522662b6c53@oss.qualcomm.com> <20260602-pdm_clk_gp_mnd_v1-v1-5-1522662b6c53@oss.qualcomm.com> In-Reply-To: <20260602-pdm_clk_gp_mnd_v1-v1-5-1522662b6c53@oss.qualcomm.com> On Tue Jun 2, 2026 at 5:21 PM CEST, Taniya Das wrote: > Add the GP M/N divider clock controller node at 0x088d3000 to the > SA8775P (kodiak, lemans) and QCS8300 (monaco) SoC device trees. forgot this in the previous email, another kodiak=3D=3Dsc7280 Regards Luca > > The node uses the qcom,clk-gp-mnd compatible, is clocked by the PDM > XO4 and AHB clocks from GCC, and exposes a single clock output > (gp_mn_clk) on the dedicated gp_mn pin mux function. The XO4 clock > is pre-assigned to 4.8 MHz (XO/4). > > Signed-off-by: Taniya Das > ---