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Miller" , "Eric Dumazet" , "Jakub Kicinski" , "Paolo Abeni" , , , "Paolo Valerio" , "Vladimir Kondratiev" , "Gregory CLEMENT" , =?utf-8?q?Beno=C3=AEt_Monin?= , "Tawfik Bayouk" , "Thomas Petazzoni" To: "Nicolai Buchwitz" From: =?utf-8?q?Th=C3=A9o_Lebrun?= Subject: Re: [PATCH net-next v5 1/3] net: macb: add QUEUE_DISABLE capability to 3 compatibles X-Mailer: aerc 0.22.0-0-gc2f86b7abde3 References: <20261016-macb-set-channels-v5-0-90ce0c0b8e75@bootlin.com> <20261016-macb-set-channels-v5-1-90ce0c0b8e75@bootlin.com> In-Reply-To: X-Last-TLS-Session-Version: TLSv1.3 Hello Nicolai, On Mon Oct 19, 2026 at 1:32 PM CEST, Nicolai Buchwitz wrote: > On 16.10.2026 18:58, Th=C3=A9o Lebrun wrote: >> From datasheets, we know those 3 IP versions support Tx and Rx queue >> disabling, ie bit 0 in RBQP and TBQP registers. > > nit: Just learned that git am will turn this into >From. Maybe reword=20 > the first sentence. Fixed! Plain text is nice but sometimes causes trouble. By the way, this patch is in a separate series now. https://lore.kernel.org/netdev/20261113-macb-caps-v1-0-42e0984b2f09@bootlin= .com/ >> All revisions I've seen either support it on both Tx & Rx or don't >> support it at all. >>=20 >> Sources: >>=20 >> Compatible | Match data | Datasheet >> =20 >> ----------------------|--------------------|------------------------- >> atmel,sama5d29-gem | sama5d29_config | DS60001764 [0] >> microchip,mpfs-macb | mpfs_config | header files [1] >> microchip,sama7g5-gem | sama7g5_gem_config | DS60001765 [2] >>=20 >> To contrast, check out the SAM9X60 DS60001579C datasheet [3] that does >> not document bit 0 as anything special on page 1041 and page 1042. >>=20 >> [0]: >> https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/Product= Documents/DataSheets/SAMA5D29-Data-Sheet-ds60001764.pdf >>=20 >> [1]: >> https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/6= 14a67ab/src/platform/drivers/mss/mss_ethernet_mac/mss_ethernet_mac_regs.h#L= 200-L207 >>=20 >> [2]: >> https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/Product= Documents/DataSheets/SAMA7G5-Series-Data-Sheet-DS60001765.pdf >>=20 >> [3]: >> https://ww1.microchip.com/downloads/en/DeviceDoc/SAM9X60-Data-Sheet-DS60= 001579C.pdf >>=20 >> Signed-off-by: Th=C3=A9o Lebrun >> --- >> drivers/net/ethernet/cadence/macb_main.c | 7 ++++--- >> 1 file changed, 4 insertions(+), 3 deletions(-) >>=20 >> diff --git a/drivers/net/ethernet/cadence/macb_main.c=20 >> b/drivers/net/ethernet/cadence/macb_main.c >> index 020a47353d01..625171fd3f9b 100644 >> --- a/drivers/net/ethernet/cadence/macb_main.c >> +++ b/drivers/net/ethernet/cadence/macb_main.c >> @@ -5743,7 +5743,7 @@ static const struct macb_config sama5d2_config =3D= =20 >> { >>=20 >> static const struct macb_config sama5d29_config =3D { >> .caps =3D MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_GEM_HAS_PTP = | >> - MACB_CAPS_USRIO_HAS_MII, >> + MACB_CAPS_USRIO_HAS_MII | MACB_CAPS_QUEUE_DISABLE, > > AFAIU this also switches WoL suspend on these SoCs from the tieoff ring= =20 > to > QUEUE_DISABLE. Was WoL tested on any of them? Worth a line in the commit > message too. Not tested, I don't have them. I've added a paragraph to the commit message to explicit this behavior change. Thanks for the review, -- Th=C3=A9o Lebrun, Bootlin Embedded Linux and Kernel engineering https://bootlin.com