From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
To: Jon Hunter <jonathanh@nvidia.com>,
Thierry Reding <treding@nvidia.com>,
"Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>,
Andrew Lunn <andrew@lunn.ch>, Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Heiner Kallweit <hkallweit1@gmail.com>,
Jakub Kicinski <kuba@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-stm32@st-md-mailman.stormreply.com,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
netdev@vger.kernel.org, Paolo Abeni <pabeni@redhat.com>
Subject: [PATCH RFC net-next 1/3] net: phylink: add config of PHY receive clock-stop in phylink_resume()
Date: Tue, 04 Mar 2025 10:53:21 +0000 [thread overview]
Message-ID: <E1tpPtp-005SoU-7N@rmk-PC.armlinux.org.uk> (raw)
In-Reply-To: <Z8bbnSG67rqTj0pH@shell.armlinux.org.uk>
Add configuration of the receive clock-stop in phylink_resume() to
ensure that the clock-stop is correctly configured.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/phy/phylink.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index a3b186ab3854..0aae0bb2a254 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -2264,7 +2264,7 @@ static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy,
pl->mac_tx_clk_stop = phy_eee_tx_clock_stop_capable(phy) > 0;
if (pl->mac_supports_eee_ops) {
- /* Explicitly configure whether the PHY is allowed to stop it's
+ /* Explicitly configure whether the PHY is allowed to stop its
* receive clock.
*/
ret = phy_eee_rx_clock_stop(phy,
@@ -2645,8 +2645,22 @@ EXPORT_SYMBOL_GPL(phylink_suspend);
*/
void phylink_resume(struct phylink *pl)
{
+ int ret;
+
ASSERT_RTNL();
+ if (pl->mac_supports_eee_ops && pl->phydev) {
+ /* Explicitly configure whether the PHY is allowed to stop its
+ * receive clock on resume to ensure that it is correctly
+ * configured.
+ */
+ ret = phy_eee_rx_clock_stop(pl->phydev,
+ pl->config->eee_rx_clk_stop_enable);
+ if (ret == -EOPNOTSUPP)
+ phylink_warn(pl, "failed to set rx clock stop: %pe\n",
+ ERR_PTR(ret));
+ }
+
if (test_bit(PHYLINK_DISABLE_MAC_WOL, &pl->phylink_disable_state)) {
/* Wake-on-Lan enabled, MAC handling */
--
2.30.2
next prev parent reply other threads:[~2025-03-04 10:53 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-04 10:53 [PATCH RFC net-next 0/3] net: stmmac: approach 2 to solve EEE LPI reset issues Russell King (Oracle)
2025-03-04 10:53 ` Russell King (Oracle) [this message]
2025-03-04 10:53 ` [PATCH RFC net-next 2/3] net: phylink: add functions to block/unblock rx clock stop Russell King (Oracle)
2025-03-04 10:53 ` [PATCH RFC net-next 3/3] net: stmmac: block PHY rx clock-stop over reset Russell King (Oracle)
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