From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from pandora.armlinux.org.uk (pandora.armlinux.org.uk [78.32.30.218]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71FCF3A1D10 for ; Wed, 4 Mar 2026 10:22:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=78.32.30.218 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772619769; cv=none; b=E448WjLj8FkSWmtQmr2QmiSa1SozSOztDIOdHFNPR20Nts3+9+tCIWbMtnInWOOMDp/PKWw6J9spywjn1HLsnvjagDM5ZY4IOGm/NKTUpO6RK3EFAFv/Oo+wSDBsDpFb0lLAgM/xCygx5WBODoDBU8cdkJIncQp5ZUsUZbk1GG0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772619769; c=relaxed/simple; bh=+pSLzm7YsrHaOBtZEmKqLdYcL2pnGiaXCoC2n124K10=; h=In-Reply-To:References:From:To:Cc:Subject:MIME-Version: Content-Disposition:Content-Type:Message-Id:Date; b=NBY99oojtWxKQyzuI86zdq+Q835prQ9Xr9Z3FHsOOoWSfAZjr+5bM1u9b1D8Cpz3MDtnnTtzDoJpY4BHCG4VTq8cfEdobjlX4Xxcr1gks11Eg+H87J/VMblaMXuSghtRtIs8im3yDKVstmnZP/0juzGeM1/BMIOc+biTzGr3Is0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=armlinux.org.uk; spf=none smtp.mailfrom=armlinux.org.uk; dkim=pass (2048-bit key) header.d=armlinux.org.uk header.i=@armlinux.org.uk header.b=OFEyZFO5; arc=none smtp.client-ip=78.32.30.218 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=armlinux.org.uk Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=armlinux.org.uk Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=armlinux.org.uk header.i=@armlinux.org.uk header.b="OFEyZFO5" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=armlinux.org.uk; s=pandora-2019; h=Date:Sender:Message-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Subject:Cc:To:From:References: In-Reply-To:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=bckk18FEL/WKB1zH3bibgFcRIdBT/iIOu/cwDyzcVjY=; b=OFEyZFO5HE41yX5nhXxqt2sCzA 5aR1EEeoZwn5WRlZT/qBFP4gdnoz++XNscEEgCchKGJ8uvEqOpWygNiXZDfsDK55+EOJeLG+pcaSK cDC2wFhs7J0s7XAaf2ze6l9XNxqTPa5kIyiXbm1UylU+30MOxxMl6X2vrFhfimt0yKjtpXyfqwWpS WhJaoZ6KCuvRJ0TTWK/q42U5fG23O48qfotZRMSA3kqvwi4G8zlsrLBT0DQds/UCtI1RuLonpHbca J/9nJb3aj8Uq4hvtuWerqEXFoDAOAF7mPlUI1iJs/dRXDND4U2FGrf1bOxywRfdkETE2syViumrU+ hnU2Q4tQ==; Received: from e0022681537dd.dyn.armlinux.org.uk ([fd8f:7570:feb6:1:222:68ff:fe15:37dd]:33524 helo=rmk-PC.armlinux.org.uk) by pandora.armlinux.org.uk with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vxjNF-000000006L8-2sV0; Wed, 04 Mar 2026 10:22:37 +0000 Received: from rmk by rmk-PC.armlinux.org.uk with local (Exim 4.98.2) (envelope-from ) id 1vxjNE-0000000Br0z-35Xu; Wed, 04 Mar 2026 10:22:36 +0000 In-Reply-To: References: From: "Russell King (Oracle)" To: Andrew Lunn Cc: Alexandre Torgue , Andrew Lunn , Chen-Yu Tsai , "David S. Miller" , Eric Dumazet , Jakub Kicinski , linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-sunxi@lists.linux.dev, netdev@vger.kernel.org, Paolo Abeni , Samuel Holland Subject: [PATCH net-next 2/8] net: stmmac: mdio: use same test for MDC clock divisor lookups Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" Message-Id: Sender: Russell King Date: Wed, 04 Mar 2026 10:22:36 +0000 Use the same frequency test for all clk_csr value lookups (clock rate > table rate). This has the side effect that the standard rate table results in the divider being used for the maximum frequency for the divider rather than the next higher divider. This still allows MDC to meet the IEE 802.3 specification, but at a rate closer to 2.5MHz for these frequencies. Signed-off-by: Russell King (Oracle) --- drivers/net/ethernet/stmicro/stmmac/common.h | 1 + .../net/ethernet/stmicro/stmmac/stmmac_mdio.c | 27 +++++++++---------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index 42a48f655849..e4ce1167ebab 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -257,6 +257,7 @@ struct stmmac_safety_stats { (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long)) /* CSR Frequency Access Defines*/ +#define CSR_F_20M 20000000 #define CSR_F_35M 35000000 #define CSR_F_60M 60000000 #define CSR_F_100M 100000000 diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c index c4123d2260bd..6292911fb54b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c @@ -484,15 +484,16 @@ struct stmmac_clk_rate { * clock frequencies. */ static const struct stmmac_clk_rate stmmac_std_csr_to_mdc[] = { - { CSR_F_35M, STMMAC_CSR_20_35M }, - { CSR_F_60M, STMMAC_CSR_35_60M }, - { CSR_F_100M, STMMAC_CSR_60_100M }, - { CSR_F_150M, STMMAC_CSR_100_150M }, - { CSR_F_250M, STMMAC_CSR_150_250M }, - { CSR_F_300M, STMMAC_CSR_250_300M }, - { CSR_F_500M, STMMAC_CSR_300_500M }, - { CSR_F_800M, STMMAC_CSR_500_800M }, - { }, + { CSR_F_800M, ~0 }, + { CSR_F_500M, STMMAC_CSR_500_800M }, + { CSR_F_300M, STMMAC_CSR_300_500M }, + { CSR_F_250M, STMMAC_CSR_250_300M }, + { CSR_F_150M, STMMAC_CSR_150_250M }, + { CSR_F_100M, STMMAC_CSR_100_150M }, + { CSR_F_60M, STMMAC_CSR_60_100M }, + { CSR_F_35M, STMMAC_CSR_35_60M }, + { CSR_F_20M, STMMAC_CSR_20_35M }, + { 0, ~0 }, }; /* The sun8i clk_csr_i to GMII_Address CR field mapping uses rate as the @@ -548,13 +549,12 @@ static u32 stmmac_clk_csr_set(struct stmmac_priv *priv) * divider. */ for (i = 0; stmmac_std_csr_to_mdc[i].rate; i++) - if (clk_rate < stmmac_std_csr_to_mdc[i].rate) { - value = stmmac_std_csr_to_mdc[i].cr; + if (clk_rate > stmmac_std_csr_to_mdc[i].rate) break; - } + if (stmmac_std_csr_to_mdc[i].cr != (u8)~0) + value = stmmac_std_csr_to_mdc[i].cr; if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) { - /* Note the different test - this is intentional. */ for (i = 0; stmmac_sun8i_csr_to_mdc[i].rate; i++) if (clk_rate > stmmac_sun8i_csr_to_mdc[i].rate) break; @@ -562,7 +562,6 @@ static u32 stmmac_clk_csr_set(struct stmmac_priv *priv) } if (priv->plat->core_type == DWMAC_CORE_XGMAC) { - /* Note the different test - this is intentional. */ for (i = 0; stmmac_xgmac_csr_to_mdc[i].rate; i++) if (clk_rate > stmmac_xgmac_csr_to_mdc[i].rate) break; -- 2.47.3