From: Andrew Lunn <andrew@lunn.ch>
To: Maxime Chevallier <maxime.chevallier@bootlin.com>
Cc: Sean Anderson <seanga2@gmail.com>,
davem@davemloft.net, Rob Herring <robh+dt@kernel.org>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
thomas.petazzoni@bootlin.com, Jakub Kicinski <kuba@kernel.org>,
Eric Dumazet <edumazet@google.com>,
Paolo Abeni <pabeni@redhat.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
linux-arm-kernel@lists.infradead.org,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
devicetree@vger.kernel.org
Subject: Re: [PATCH net-next v3 3/5] net: pcs: add new PCS driver for altera TSE PCS
Date: Wed, 26 Oct 2022 14:05:25 +0200 [thread overview]
Message-ID: <Y1kihVfwglzOD2uE@lunn.ch> (raw)
In-Reply-To: <20221026113711.2b740c7a@pc-8.home>
> > > + /* This PCS seems to require a soft reset to re-sync the
> > > AN logic */
> > > + tse_pcs_reset(tse_pcs);
> >
> > This is kinda strange since c22 phys are supposed to reset the other
> > registers to default values when BMCR_RESET is written. Good thing
> > this is a PCS...
>
> Indeed. This soft reset will not affect the register configuration, it
> will only reset all internal state machines.
>
> The datasheet actually recommends performing a reset after any
> configuration change...
The Marvell PHYs work like this. Many of its registers won't take
effect until you do a soft reset. I think the thinking behind this is
that changing many registers is disruptive to the link and slow. It
takes over a second to perform auto-neg etc. So ideally you want to
make all your register changes, and then trigger them into operation.
And a soft reset is this trigger.
Andrew
next prev parent reply other threads:[~2022-10-26 12:08 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-01 14:35 [PATCH net-next v3 0/5] net: altera: tse: phylink conversion Maxime Chevallier
2022-09-01 14:35 ` [PATCH net-next v3 1/5] dt-bindings: net: Convert Altera TSE bindings to yaml Maxime Chevallier
2022-09-01 14:35 ` [PATCH net-next v3 2/5] net: altera: tse: cosmetic change to use reverse xmas tree ordering Maxime Chevallier
2022-09-01 14:35 ` [PATCH net-next v3 3/5] net: pcs: add new PCS driver for altera TSE PCS Maxime Chevallier
2022-10-09 5:38 ` Sean Anderson
2022-10-26 9:37 ` Maxime Chevallier
2022-10-26 12:05 ` Andrew Lunn [this message]
2022-10-26 12:47 ` Russell King (Oracle)
2022-09-01 14:35 ` [PATCH net-next v3 4/5] net: altera: tse: convert to phylink Maxime Chevallier
2022-09-02 4:10 ` Jakub Kicinski
2022-09-02 7:57 ` Maxime Chevallier
2022-09-01 14:35 ` [PATCH net-next v3 5/5] dt-bindings: net: altera: tse: add an optional pcs register range Maxime Chevallier
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