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From: Andrew Lunn <andrew@lunn.ch>
To: Jan Petrous <jan.petrous@nxp.com>
Cc: "Chester Lin" <clin@suse.com>,
	"Andreas Färber" <afaerber@suse.de>,
	"Rob Herring" <robh@kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	"Eric Dumazet" <edumazet@google.com>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Paolo Abeni" <pabeni@redhat.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	dl-S32 <S32@nxp.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"Matthias Brugger" <mbrugger@suse.com>
Subject: Re: [EXT] Re: [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver
Date: Thu, 10 Nov 2022 14:04:09 +0100	[thread overview]
Message-ID: <Y2z2yeQpMQV4y+4H@lunn.ch> (raw)
In-Reply-To: <AM9PR04MB8506F52B7E88ED1FE64554A1E2019@AM9PR04MB8506.eurprd04.prod.outlook.com>

On Thu, Nov 10, 2022 at 08:51:43AM +0000, Jan Petrous wrote:
> Hi Andrew,
> 
> > > > Here I just focus on GMAC since there are other LAN interfaces that S32
> > > > family
> > > > uses [e.g. PFE]. According to the public GMACSUBSYS ref manual rev2[1]
> > > > provided
> > > > on NXP website, theoretically GMAC can run SGMII in 1000Mbps and
> > > > 2500Mbps so I
> > > > assume that supporting 1000BASE-X could be achievable. I'm not sure if
> > any
> > > > S32
> > > > board variant might have SFP ports but RJ-45 [1000BASE-T] should be the
> > > > major
> > > > type used on S32G-EVB and S32G-RDB2.
> > > >
> > > > @NXP, please feel free to correct me if anything wrong.
> > > >
> > >
> > > NXP eval boards (EVB or RDB) have also 2.5G PHYs, so together with SerDes
> > > driver we support 100M/1G/2.5G on such copper PHYs.
> > 
> > Hi Jan
> > 
> > Does the SERDES clock need to change when going between 1000BaseX and
> > 2500BaseX?
> > 
> > If so, it sounds like Linux not having control of that clock is going
> > to limit what can be supported.
> 
> No, the SerDes clock remains the same, the change is done internally, without
> any necessity of clock change intervention by GMAC driver.

Hi Jan

Thanks for the information. So this binding should work.

The only suggestion i have is that the binding does not call is SGMII
clock, because it is used for more than SGMII, also 1000base-X, and
2500Base-X. So PCS clock might be better.

	Andrew	    

  reply	other threads:[~2022-11-10 13:05 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-31 10:10 [PATCH 0/5] Add GMAC support for S32 SoC family Chester Lin
2022-10-31 10:10 ` [PATCH 1/5] dt-bindings: net: snps, dwmac: add NXP S32CC support Chester Lin
2022-10-31 10:10 ` [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver Chester Lin
2022-11-02 15:55   ` Rob Herring
2022-11-02 17:13     ` Andreas Färber
2022-11-02 21:44       ` Rob Herring
2022-11-04 10:11         ` Chester Lin
2022-11-03 22:05       ` Andrew Lunn
2022-11-04 11:39         ` Chester Lin
2022-11-04 13:30           ` Andrew Lunn
2022-11-09  8:09             ` Chester Lin
2022-11-09 22:55           ` [EXT] " Jan Petrous
2022-11-09 23:00             ` Andrew Lunn
2022-11-10  8:51               ` Jan Petrous
2022-11-10 13:04                 ` Andrew Lunn [this message]
2022-11-09 22:55       ` Jan Petrous
2022-10-31 10:10 ` [PATCH 3/5] net: stmmac: Add CSR clock 500Mhz/800Mhz support Chester Lin
2022-10-31 10:10 ` [PATCH 4/5] net: stmmac: Add AXI4 ACE control support Chester Lin
2022-10-31 10:10 ` [PATCH 5/5] net: stmmac: Add NXP S32 SoC family support Chester Lin
2022-10-31 13:27   ` Andrew Lunn

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