From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D11A8C4332F for ; Fri, 18 Nov 2022 00:07:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240332AbiKRAHo (ORCPT ); Thu, 17 Nov 2022 19:07:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232050AbiKRAHn (ORCPT ); Thu, 17 Nov 2022 19:07:43 -0500 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02584D94; Thu, 17 Nov 2022 16:07:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=wv0rvg+qGKsAcuFlpcEuCbIUu5ZxBnWHri6DHVe34qM=; b=eJpO91RR72W5+FtReIbXj9YpnF UgtpfDtz73IFT43IR566O3HGWcpc1IAtBKPeRKMfyNoAr4+c/foJCODDoijtPztc7lWW8z6Y7odrA KyKEkvMb+1cMD+oi95YAvMEJWY+Xj39t5LMghRPcpOef96VANYI9IASt5OItnjdn1Mfs=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1ovouw-002kA8-Id; Fri, 18 Nov 2022 01:07:38 +0100 Date: Fri, 18 Nov 2022 01:07:38 +0100 From: Andrew Lunn To: Andy Chiu Cc: davem@davemloft.net, kuba@kernel.org, michal.simek@xilinx.com, radhey.shyam.pandey@xilinx.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, pabeni@redhat.com, edumazet@google.com, greentime.hu@sifive.com Subject: Re: [PATCH v5 net-next 3/3] net: axienet: set mdio clock according to bus-frequency Message-ID: References: <20221117154014.1418834-1-andy.chiu@sifive.com> <20221117154014.1418834-4-andy.chiu@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221117154014.1418834-4-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Thu, Nov 17, 2022 at 11:40:14PM +0800, Andy Chiu wrote: > Some FPGA platforms have 80KHz MDIO bus frequency constraint when > connecting Ethernet to its on-board external Marvell PHY. Thus, we may > have to set MDIO clock according to the DT. Otherwise, use the default > 2.5 MHz, as specified by 802.3, if the entry is not present. > > Also, change MAX_MDIO_FREQ to DEFAULT_MDIO_FREQ because we may actually > set MDIO bus frequency higher than 2.5MHz if undelying devices support > it. And properly disable the mdio bus clock in error path. > > Signed-off-by: Andy Chiu Reviewed-by: Andrew Lunn Andrew