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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?f2s0BPMf+KIVrx24lkWsNPECdP9quguHv/zVDzjQrT+Et6NsjHPh1QmO/KJp?= =?us-ascii?Q?qpo1YDORmJH+u8AjKFuAidwHjzXzhQGMZQf1l7LRkQgfff2nSUyiuBGYXgBm?= =?us-ascii?Q?SAgbOmCyRAASx09fcsw7DwaaSQxMbGkT1C9SshJpmHtunJgRVOTAfY6v4Tke?= =?us-ascii?Q?yqj3lMKUQU5BHnrmHwpMIQ87VK9i9mA8CmgwVrpx1+gTJG0JnTq4VAYIAsnZ?= =?us-ascii?Q?j7FQSVtTgRT7aNDj3/NHP7w7qtNHKZjSKdRB2VY2jGMoOwHdNs2XnqStuttd?= =?us-ascii?Q?xiPoM4aYWdCPGslrmiTX428GBy7o3HFY/I469kk/zX+gEyuob3swE5AIVeq2?= =?us-ascii?Q?tf1hqfWX1jG6EFdvD2IqzRB3/9siLUZEIdBRWVwX8S5/0ZmkNY635uIzkYuf?= =?us-ascii?Q?AzYHhZFYw5ZacNJJ9pZaK0EBkElIGSH+JLm5aT8nFzVSYivLRxe6LngoFSmJ?= =?us-ascii?Q?CW/hoq9mlPP4XAoYWxdbu11ZZLAiudtzRCKKYzZCXZ268oUZ8m/SZq91zl81?= =?us-ascii?Q?uVpUAqIyPRAVZq7Zmss8TqN4ZULImukljVFmEEEFdtgn0tzpjMTWO2rfYOSK?= =?us-ascii?Q?3UJ6cKrt3hdWVOkeCSYbnM0vrQF4OBEMMyGqJKSEWQa1WeYwJsfX5ZbsxqC7?= =?us-ascii?Q?54Hsvs3p4/KnUa/glnG2uiaNGS3buYA6aeaHNuCvRQaGeOdjpR9F+0TGlVTn?= =?us-ascii?Q?x0tK42VNDWapMLcsus/9X8Oq7P+Dc7fOu0gIQf3nho+vCufI47uC5JigQtcC?= =?us-ascii?Q?soRZUR94Dnf6RLcNuw5ghlCe4gUt41NjSU72Om3uQ2hf2A0YWonNeY39Uwx8?= =?us-ascii?Q?K/zy7FcZlqRgkGk7aQ3X6WiXtUOmLh9An+bWCQztRt7sDKC961oDLWa3BpFV?= =?us-ascii?Q?s1cDhpgJ9rdU40etnaVPnHRcwP5dppFZKeqd3OJuOzXaZqGFsEaLawhgyXrx?= =?us-ascii?Q?WtmaPauceBmGOXh/RahMYcPVLZP/wcS2awsu9DHXEtygwTKCHu6yGV0v8wKF?= =?us-ascii?Q?Hs+Jbt8+vb2J9Tva5RhiAFKBzyQnq23UjMArzBLfaq+FgZ6viNCUXcz9JuDv?= =?us-ascii?Q?Je6w2UG2qULF/mlM6VS1IigmoLXx9DgBzW5Zl0HQs1SFX0jnZZorpgKc07Qw?= =?us-ascii?Q?47o6fe5PrYPoDhzru7WRkdSDJsKhGD+/QQNN2w72sIK6Et9SC5iyjM5j7gCK?= =?us-ascii?Q?Y+M1CSZZuiKCoJWQhWb/sDq3KHFt6Ds8zi68gzUqB0I+9ByojLsWPP1unsCI?= =?us-ascii?Q?LceJgZyp0ooem6IvWX+1qMVN1WiFBcDbVTXBUMLQs753K6tRy7/theITHmL3?= =?us-ascii?Q?1ls3bFKZqzzbybEp/R46UKz1Z7MwNFkPop9sxJXxSWlly6Wh1PInlBAXPW2P?= =?us-ascii?Q?iZ3Wxf4q+kR8jDUhIp9DNTHVpFwfpqm93HVrZezmSL9vxqRsLSHHYvKxJPH1?= =?us-ascii?Q?HdjIpZFa9nc03S345jkBr4JnRZE4jlvNXwdb7XvzevoXZG8Ww3Byo6vbeZdK?= =?us-ascii?Q?aTlM93S6PmAjVIJC1dTqjh9bl3NspyisfTnH9GRuFTSpdZlkHfAx6a4ASqXE?= =?us-ascii?Q?eveAbYUFw66rcnAnnK3pEreCOwA2/DiNq95NP5uHBaxK7U3KLdVYT1tSPKbA?= =?us-ascii?Q?Hw=3D=3D?= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 699e75ab-e317-4d11-716c-08dae53635cd X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Dec 2022 22:37:02.3591 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: J6VutHhMSWSDPPGlxU1rk7rs2xUuaVwTZAWpt9JCdp010XMT2s+Iji1sVEfpR1QHquTChpyya7jv+tPTOgBC3vBMx0ue8tW0uHCoUePc2P4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR10MB4550 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Fri, Dec 23, 2022 at 10:18:54PM +0100, Andrew Lunn wrote: > > > > What's the catch? > > > > > > I actually think you need silicon support for this. Earlier versions > > > of the Marvell Switches are missing some functionality, which results > > > in VLANs leaking in distributed setups. I think the switches also > > > share information between themselves, over the DSA ports, i.e. the > > > ports between switches. > > > > > > I've no idea if you can replicate the Marvell DSA concept with VLANs. > > > The Marvell header has D in DSA as a core concept. The SoC can request > > > a frame is sent out a specific port of a specific switch. And each > > > switch has a routing table which indicates what egress port to use to > > > go towards a specific switch. Frames received at the SoC indicate both > > > the ingress port and the ingress switch, etc. > > > > "It might not work at all" is definitely a catch :-) > > > > I haven't looked into the Marvell documentation about this, so maybe > > that's where I should go next. It seems Ocelot chips support > > double-tagging, which would lend itself to the SoC being able to > > determine which port and switch for ingress and egress... though that > > might imply it could only work with DSA ports on the first chip, which > > would be an understandable limitation. > > > > > > > > > In the Marvell case, is there any gotcha where "under these scenarios, > > > > the controlling CPU needs to process packets at line rate"? > > > > > > None that i know of. But i'm sure Marvell put a reasonable amount of > > > thought into how to make a distributed switch. There is at least one > > > patent covering the concept. It could be that a VLAN based > > > re-implemention could have such problems. > > > > I'm starting to understand why there's only one user of > > crosschip_bridge_* functions. So this sounds to me like a "don't go down > > this path - you're in for trouble" scenario. > > What is your real use case here? Fair question. We have a baseboard configuration with cards that offer customization / expansion. An example might be a card that offers additional fibre / copper ports, which would lend itself very nicely to a DSA configuration... more cards == more ports. We can see some interesting use of vlans for all sorts of things. I haven't been the boots on the ground, so I don't know all the use-cases. My main hope is to be able to offer as much configurability for the system integrators as possible. Maybe sw2p2 is a tap of sw1p2, while sw2p3, sw2p4, and sw1p3 are bridged, with the CPU doing IGMP snooping and running RSTP. > > I know people have stacked switches before, and just operated them as > stacked switches. So you need to configure each switch independently. > What Marvell DSA does is make it transparent, so to some extent it > looks like one big switch, not a collection of switches. That is definitely possible. It might make the people doing any system integration have a lot more knowledge than a simple "add this port to that bridge". My goal is to make their lives as easy as can be. It sounds like that all exists with Marvell hardware...