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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?5d+VT/jQ1KNoSQu6uAVRVl4kBbrRJmZ54qwqgBBEROn0i01hzwhLZMbXfAfA?= =?us-ascii?Q?1xSj71IswTY488oiJpkL0KuoYfSbeLxxsMDJtbDI0eYNMUHQworOKVgVyvbW?= =?us-ascii?Q?sUIxvhLZJNIB4WS2ymzQXq23QbA4JfTGzZZXok6V0Z+Nf3V8f8i3MEal/CMA?= =?us-ascii?Q?uFSv9Zz7YCXsz2BgfqgrhgUwn7Sq8FWGxIh2mimcKKJh8V+RLnxMRtnyszYt?= =?us-ascii?Q?4TyIuB+iNwhyw/fMV3OLecY0ZRtcYsV0GkKzNm5e8sV64NG7MrJUMFGmHVjy?= =?us-ascii?Q?To8/MUimhtw+j6TskLnA02MBE+zreyLp9JYkavJqGUezDNB5npEx99gGtsdV?= =?us-ascii?Q?3KT0PZ1jTNfjupe8DvA9HE/jOeV6eP58hHRGjPgU7AHsJd3lKVOtipuiJlw9?= =?us-ascii?Q?OnJzDy+buegsWDb68hM+M9zk4cpu3x8WNU6cgSu+I9ppcFJgxANhzhdkP2Si?= =?us-ascii?Q?SRSh5gsDusjVG/h8EiWGJGBTV6+vG57mE6pyedQ81gMPxVxx71VBn9mF+O0W?= =?us-ascii?Q?7bj62m+joBTQBz/IQIpIsCa8nLX66FKg52jPwFPRKEzzMogQyx7i46bTPCNu?= =?us-ascii?Q?IebTGljZr0QNo/OUOSA5rl11lETlqesLdRZ4tfLY9TmWIsTTmi02xpqWU3EB?= =?us-ascii?Q?NVjnqGW9kRsYVdrM78IlFXV3tqbjOAPCsqm3/cJmV3mPgdE6vMhLxbfyAiuv?= =?us-ascii?Q?zYFLSfdCdbqOqCXY+JbK3AX0ExvWQN3qJ1+CsxB+Hif/gUPwaFzKMWDgGn91?= =?us-ascii?Q?d3ADtqZ7WuANw//siA6e9T9KsZHmjYbysEVZluLyv6MhaOzZG9Ms/n112dHT?= =?us-ascii?Q?nKdNt6mP8owoi+/SV8g6xiSvxh8fMLmifbNuyV0k6DEBnZTJOZwj/R3dApa4?= =?us-ascii?Q?nY0i5M8A4tCoyFHeNt3hAhajJs37UEhABdJIsEyh1YecTjtpOmPAYbJSump4?= =?us-ascii?Q?DnaOmaMmx0jkSZVcCA0+oEWjGNI0Ee+Md9tgTI2JeGWpPEJvgJEnikmdbjmX?= =?us-ascii?Q?zwpoi3Q8YF4ySFtCP0kU0+it/ZaEBSI7krQyEhSLxPjftOiX6bIHwUQWdRVH?= =?us-ascii?Q?ihGy8flW36xurQmRtbpx8F7ZV9dbgmOZa5HgSd1ea85F9H9Lg8XbA3Ux/w4r?= =?us-ascii?Q?N0VR4w6sQGpkbqUSzywDGjJBraYWVIdIP3pa44af+PF8vshM/7+zrE6q0lxn?= =?us-ascii?Q?fypNe8dErQD7vmGt824lb+CR62BrXKaZvUGXQAFKSypl3za7OPhxTGr9gPjo?= =?us-ascii?Q?XxNQhAaI13XFeVQT0bgpp+LByF+06eKrZR4Xbri6uKyef1gJC6KsK1jmKWwe?= =?us-ascii?Q?00fObq1bwjp358M/mbaEGomx4ylhB1h4RgghzKN0BOFrdefTEc65+o4f6omc?= =?us-ascii?Q?A+XajMxIMhvUU4mcEcxrVLQrSlsV/YvVgcNGFlwA3iVE8NXVfrp9gHTE+dhN?= =?us-ascii?Q?oUqMYL9uETZd2Hjmb/l+IZsJoCqzvYaKkfZIOhRWpednhL3+9HeT2xuWpXND?= =?us-ascii?Q?klcXYOo/Tf4i+fWq+0iq0OVXLN/zlUMRUMb/3yNZeXgAmmNmGuNQckhBYvQ7?= =?us-ascii?Q?POu0YaHdusMyhHd2qoXK12npFD0M3j3jjkqKhiBcHCj32bDsASFrcM/WABvD?= =?us-ascii?Q?Qw=3D=3D?= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: e07a250a-7c84-4cee-97d5-08dae5e01c11 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Dec 2022 18:53:13.5040 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iBAivpMQSgl1lvaMUXvGrSmSp7lGUZDzEEAPXXmClRKYbLhicVRWia5P/KOf6rsInIfTxaMyccSUcVjnjG/QRW01JFaJFRg2tcu5O3L6HN8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR10MB4937 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Sat, Dec 24, 2022 at 02:59:34AM +0200, Vladimir Oltean wrote: > Hi Colin, > > On Fri, Dec 23, 2022 at 12:54:29PM -0800, Colin Foster wrote: > > On Fri, Dec 23, 2022 at 09:05:27PM +0100, Andrew Lunn wrote: > > I'm starting to understand why there's only one user of > > crosschip_bridge_* functions. So this sounds to me like a "don't go down > > this path - you're in for trouble" scenario. > > Trying to build on top of what Andrew has already replied. > > Back when I was new to DSA and completely unqualified to be a DSA reviewer/ > maintainer (it's debatable whether now I am), I actually had some of the > same questions about what's possible in terms of software support, given > the Vitesse architectural limitations for cross-chip bridging a la Marvell, > in this email thread: > https://patchwork.kernel.org/project/linux-arm-kernel/patch/1561131532-14860-5-git-send-email-claudiu.manoil@nxp.com/ Thank you for this link. I'll look it over. As usual, I'll need some time to absorb all this information :-) > > That being said, you need to broaden your detection criteria for cross-chip > bridging; sja1105 (and tag_8021q in general) supports this too, except > it's a bit hidden from the ds->ops->crosschip_bridge_join() operation. > It all relies on the concept of cross-chip notifier chain from switch.c. > dsa_tag_8021q_bridge_join() will emit a DSA_NOTIFIER_TAG_8021Q_VLAN_ADD > event, which the other tag_8021q capable switches in the system will see > and react to. > > Because felix and sja1105 each support a tagger based on tag_8021q for > different needs, there is an important difference in their implementations. > The comment in dsa_tag_8021q_bridge_join() - called by sja1105 but not > by felix - summarizes the essence of the difference. Hmm... So the Marvell and sja1105 both support "Distributed" but in slightly different ways? > > If Felix were to gain support for tag_8021q cross-chip bridging*, the > driver would would need to look at the switch's position within the PCB topology. > On the user ports, tag_8021q would have to be implemented using the VCAP > TCAM rules, to retain support for VLAN-aware bridging and just push/pop the > VLAN that serves as make-shift tag. On the DSA "cascade" ports, tag_8021q > would have to be implemented using the VLAN table, in order to make the > switch understand the tag that's already in the packet and route based > on it, rather than push yet another one. The proper combination of VCAP > rules and VLAN table entries needs much more consideration to cover all > scenarios (CPU RX over a daisy chain; CPU TX over a daisy chain; > autonomous forwarding over 2 switches; autonomous forwarding over 3 > switches; autonomous forwarding between sja1105 and felix; forwarding > done by felix for traffic originated by one sja1105 and destined to > another sja1105; forwarding done by felix for traffic originated by a > sja1105 and destined to a felix user port with no other downstream switch). ^ This paragraph is what I need! Although I'm leaning very much torward the "run away" solution (and buying some fun hardware in the process) this is something I'll keep revisiting as I learn. If it isn't fall-off-a-log easy for you, I probably don't stand a chance. > > You might find some of my thoughts on this topic interesting, in the > "Switch topology changes" chapter of this PDF: > https://lpc.events/event/11/contributions/949/attachments/823/1555/paper.pdf I'm well aware of this paper :-) I'll give it another re-read, as I always find new things. > > With that development summary in mind, you'll probably be prepared to > use "git log" to better understand some of the stages that tag_8021q > cross-chip bridging has been through. Yes, a couple key terms and a little background can go a very long way! Thanks. > > In principle, when comparing tag_8021q cross-chip bridging to something > proprietary like Marvell, I consider it to be somewhat analogous to > Russian/SSSR engineering: it's placed on the "good" side of the diminishing > returns curve, or i.o.w., it works stupidly well for how simplistic it is. > I could be interested to help if you come up with a sound proposal that > addresses your needs and is generic enough that pieces of it are useful > to others too. Great to know. I'm in a very early "theory only" stage of this. First things first - I need to button up full switch functionality and add another year to the Copyright notice. > > *I seriously doubt that any hw manufacturer would be crazy enough to > use Vitesse switches for an application for which they are essentially > out of spec and out of their intended use. Yet that is more or less the > one-sentence description of what we, at NXP, are doing with them, so I > know what it's like and I don't necessarily discourage it ;) Generally > I'd say they take a bit of pushing quite well (while failing at some > arguably reasonable and basic use cases, like flow control on NPI port - > go figure).