From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFCD1C433DB for ; Sun, 24 Jan 2021 18:52:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ADAB622D50 for ; Sun, 24 Jan 2021 18:52:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726458AbhAXSwA (ORCPT ); Sun, 24 Jan 2021 13:52:00 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:56988 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726177AbhAXSv6 (ORCPT ); Sun, 24 Jan 2021 13:51:58 -0500 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1l3kTh-002PUt-OC; Sun, 24 Jan 2021 19:51:13 +0100 Date: Sun, 24 Jan 2021 19:51:13 +0100 From: Andrew Lunn To: Russell King - ARM Linux admin Cc: stefanc@marvell.com, netdev@vger.kernel.org, thomas.petazzoni@bootlin.com, davem@davemloft.net, nadavh@marvell.com, ymarkman@marvell.com, linux-kernel@vger.kernel.org, kuba@kernel.org, mw@semihalf.com, atenart@kernel.org Subject: Re: [PATCH v2 RFC net-next 03/18] net: mvpp2: add CM3 SRAM memory map Message-ID: References: <1611488647-12478-1-git-send-email-stefanc@marvell.com> <1611488647-12478-4-git-send-email-stefanc@marvell.com> <20210124124443.GX1551@shell.armlinux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210124124443.GX1551@shell.armlinux.org.uk> Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Sun, Jan 24, 2021 at 12:44:43PM +0000, Russell King - ARM Linux admin wrote: > On Sun, Jan 24, 2021 at 01:43:52PM +0200, stefanc@marvell.com wrote: > > + priv->sram_pool = of_gen_pool_get(dn, "cm3-mem", 0); > > + if (!priv->sram_pool) { > > + if (!defer_once) { > > + defer_once = true; > > + /* Try defer once */ > > + return -EPROBE_DEFER; > > + } > > + dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n"); > > + return -ENOMEM; > > + } > > + priv->cm3_base = (void __iomem *)gen_pool_alloc(priv->sram_pool, > > + MSS_SRAM_SIZE); > > + if (!priv->cm3_base) > > + return -ENOMEM; > > This probably could do with a comment indicating that it is reliant on > this allocation happening at offset zero into the SRAM. The only reason > that is guaranteed _at the moment_ is because the SRAM mapping is 0x800 > bytes in size, and you are requesting 0x800 bytes in this allocation, > so allocating the full size. Hi Russell I'm wondering if using a pool even makes sense. The ACPI case just ioremap() the memory region. Either this memory is dedicated, and then there is no need to use a pool, or the memory is shared, and at some point the ACPI code is going to run into problems when some other driver also wants access. Andrew