From: Andrew Lunn <andrew@lunn.ch>
To: Joakim Zhang <qiangqing.zhang@nxp.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>,
netdev <netdev@vger.kernel.org>, dl-linux-imx <linux-imx@nxp.com>
Subject: Re: [PATCH V1 net-next 0/3] net: stmmac: implement clocks
Date: Thu, 25 Feb 2021 14:14:16 +0100 [thread overview]
Message-ID: <YDeiqACL9Rtja6tH@lunn.ch> (raw)
In-Reply-To: <DB8PR04MB679510F099C88F6B4BA10970E69E9@DB8PR04MB6795.eurprd04.prod.outlook.com>
> Hi Andrew,
>
> Thanks for you explanation, I still don't quite understand what the use case it is, could you give me more details, thanks a lot!
> AFAIK now, there are two connections methods, we can abstract the layer:
> MAC <-> MAC, there is no PHY attached. It seems to know as Fixed link, right?
Yes, this is the most common way of connecting a switch.
> MAC+PHY <-> PHY+MAC
Switches can be connected like this, but not often. Why pay for two
PHYs which you do not need?
> From your expression, you should use an external Ethernet switch, if
> yes, why Ethernet switch needs to use MDIO bus to access another
> MAC's(STMMAC) PHY?
The switch is on the same board as the MAC. Take a look at:
https://netdevconf.info/2.1/papers/distributed-switch-architecture.pdf
It explains the DSA architecture.
Andrew
prev parent reply other threads:[~2021-02-25 13:15 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-23 10:48 [PATCH V1 net-next 0/3] net: stmmac: implement clocks Joakim Zhang
2021-02-23 10:48 ` [PATCH V1 net-next 1/3] net: stmmac: add clocks management for gmac driver Joakim Zhang
2021-02-23 16:46 ` Jakub Kicinski
2021-02-24 1:46 ` Joakim Zhang
2021-02-23 10:48 ` [PATCH V1 net-next 2/3] net: stmmac: add platform level clocks management Joakim Zhang
2021-02-23 10:48 ` [PATCH V1 net-next 3/3] net: stmmac: add platform level clocks management for i.MX Joakim Zhang
2021-02-23 16:45 ` [PATCH V1 net-next 0/3] net: stmmac: implement clocks Jakub Kicinski
2021-02-24 1:45 ` Joakim Zhang
2021-02-24 1:54 ` Jakub Kicinski
2021-02-24 2:13 ` Joakim Zhang
2021-02-24 2:34 ` Jakub Kicinski
2021-02-24 2:47 ` Joakim Zhang
2021-02-24 3:54 ` Florian Fainelli
2021-02-25 1:42 ` Joakim Zhang
2021-02-24 9:03 ` Joakim Zhang
2021-02-24 13:01 ` Andrew Lunn
2021-02-25 2:15 ` Joakim Zhang
[not found] ` <DB8PR04MB6795FAE4C1736AABDCA75FA7E69E9@DB8PR04MB6795.eurprd04.prod.outlook.com>
2021-02-25 2:33 ` Andrew Lunn
2021-02-25 11:48 ` Joakim Zhang
2021-02-25 13:14 ` Andrew Lunn [this message]
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