From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFB2AC433DB for ; Fri, 26 Mar 2021 12:15:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6779A61A2A for ; Fri, 26 Mar 2021 12:15:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229969AbhCZMO5 (ORCPT ); Fri, 26 Mar 2021 08:14:57 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:49026 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229848AbhCZMOx (ORCPT ); Fri, 26 Mar 2021 08:14:53 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1lPlMW-00D7sR-R8; Fri, 26 Mar 2021 13:14:48 +0100 Date: Fri, 26 Mar 2021 13:14:48 +0100 From: Andrew Lunn To: Robert Hancock Cc: davem@davemloft.net, kuba@kernel.org, radhey.shyam.pandey@xilinx.com, robh@kernel.org, devicetree@vger.kernel.org, netdev@vger.kernel.org Subject: Re: [PATCH net-next v4 2/2] net: axienet: Enable more clocks Message-ID: References: <20210326000438.2292548-1-robert.hancock@calian.com> <20210326000438.2292548-3-robert.hancock@calian.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210326000438.2292548-3-robert.hancock@calian.com> Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Thu, Mar 25, 2021 at 06:04:38PM -0600, Robert Hancock wrote: > This driver was only enabling the first clock on the device, regardless > of its name. However, this controller logic can have multiple clocks > which should all be enabled. Add support for enabling additional clocks. > The clock names used are matching those used in the Xilinx version of this > driver as well as the Xilinx device tree generator, except for mgt_clk > which is not present there. > > For backward compatibility, if no named clocks are present, the first > clock present is used for determining the MDIO bus clock divider. > > Reviewed-by: Radhey Shyam Pandey > Signed-off-by: Robert Hancock Reviewed-by: Andrew Lunn Andrew