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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2021 09:04:29.6482 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a625d7d4-80b8-44ca-fa7d-08d98b03cd70 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1201MB0247 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Fri, Oct 08, 2021 at 03:57:36PM -0300, Jason Gunthorpe wrote: > On Fri, Oct 08, 2021 at 03:24:26PM +0300, Mark Zhang wrote: > > > > Aharon Landau (12): > > net/mlx5: Add ifc bits to support optional counters > > net/mlx5: Add priorities for counters in RDMA namespaces > > RDMA/counter: Add a descriptor in struct rdma_hw_stats > > RDMA/counter: Add an is_disabled field in struct rdma_hw_stats > > RDMA/counter: Add optional counter support > > RDMA/nldev: Add support to get status of all counters > > RDMA/nldev: Split nldev_stat_set_mode_doit out of nldev_stat_set_doit > > RDMA/nldev: Allow optional-counter status configuration through RDMA > > netlink > > RDMA/mlx5: Support optional counters in hw_stats initialization > > RDMA/mlx5: Add steering support in optional flow counters > > RDMA/mlx5: Add modify_op_stat() support > > RDMA/mlx5: Add optional counter support in get_hw_stats callback > > > > Mark Zhang (1): > > RDMA/core: Add a helper API rdma_free_hw_stats_struct > > This seems fine now, please update the shared branch Thanks, applied b8dfed636fc6 net/mlx5: Add priorities for counters in RDMA namespaces 8208461d3912 net/mlx5: Add ifc bits to support optional counters > > Jason