From: Ido Schimmel <idosch@idosch.org>
To: "Machnikowski, Maciej" <maciej.machnikowski@intel.com>
Cc: Petr Machata <petrm@nvidia.com>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"intel-wired-lan@lists.osuosl.org"
<intel-wired-lan@lists.osuosl.org>,
"Kubalewski, Arkadiusz" <arkadiusz.kubalewski@intel.com>,
"richardcochran@gmail.com" <richardcochran@gmail.com>,
"abyagowi@fb.com" <abyagowi@fb.com>,
"Nguyen, Anthony L" <anthony.l.nguyen@intel.com>,
"davem@davemloft.net" <davem@davemloft.net>,
"kuba@kernel.org" <kuba@kernel.org>,
"linux-kselftest@vger.kernel.org"
<linux-kselftest@vger.kernel.org>,
"mkubecek@suse.cz" <mkubecek@suse.cz>,
"saeed@kernel.org" <saeed@kernel.org>,
"michael.chan@broadcom.com" <michael.chan@broadcom.com>
Subject: Re: [PATCH v4 net-next 2/4] ethtool: Add ability to configure recovered clock for SyncE feature
Date: Fri, 3 Dec 2021 17:58:20 +0200 [thread overview]
Message-ID: <Yao+nK40D0+u8UKL@shredder> (raw)
In-Reply-To: <MW5PR11MB581202E2A601D34E30F1E5AEEA6A9@MW5PR11MB5812.namprd11.prod.outlook.com>
On Fri, Dec 03, 2021 at 02:55:05PM +0000, Machnikowski, Maciej wrote:
> If you have 32 port switch chip with 2 recovered clock outputs how will you
> tell the chip to get the 18th port to pin 0 and from port 20 to pin 1? That's
> the part those patches addresses. The further side of "which clock should the
> EEC use" belongs to the DPLL subsystem and I agree with that.
>
> Or to put it into different words:
> This API will configure given quality level frequency reference outputs on chip's
> Dedicated outputs. On a board you will connect those to the EEC's reference inputs.
So these outputs are hardwired into the EEC's inputs and are therefore
only meaningful as EEC inputs? If so, why these outputs are not
configured via the EEC object?
>
> The EEC's job is to validate the inputs and lock to them following certain rules,
> The PHY/MAC (and this API) job is to deliver reference signals to the EEC.
>
next prev parent reply other threads:[~2021-12-03 15:58 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-01 18:02 [PATCH v4 net-next 0/4] Add ethtool interface for SyncE Maciej Machnikowski
2021-12-01 18:02 ` [PATCH v4 net-next 1/4] ice: add support detecting features based on netlist Maciej Machnikowski
2021-12-01 18:02 ` [PATCH v4 net-next 2/4] ethtool: Add ability to configure recovered clock for SyncE feature Maciej Machnikowski
2021-12-02 11:48 ` kernel test robot
2021-12-02 12:43 ` Ido Schimmel
2021-12-02 15:17 ` Machnikowski, Maciej
2021-12-02 16:35 ` Ido Schimmel
2021-12-02 17:20 ` Machnikowski, Maciej
2021-12-03 14:26 ` Petr Machata
2021-12-03 14:55 ` Machnikowski, Maciej
2021-12-03 15:58 ` Ido Schimmel [this message]
2021-12-03 16:26 ` Petr Machata
2021-12-03 16:50 ` Machnikowski, Maciej
2021-12-03 18:44 ` Petr Machata
2021-12-03 19:07 ` Machnikowski, Maciej
2021-12-06 14:40 ` Petr Machata
2021-12-06 15:09 ` Machnikowski, Maciej
2021-12-06 16:00 ` Petr Machata
2021-12-06 18:49 ` Machnikowski, Maciej
2021-12-03 15:45 ` Ido Schimmel
2021-12-03 16:18 ` Machnikowski, Maciej
2021-12-03 18:21 ` Petr Machata
2021-12-05 12:24 ` Ido Schimmel
2021-12-06 9:15 ` Machnikowski, Maciej
2021-12-01 18:02 ` [PATCH v4 net-next 3/4] ice: add support for monitoring SyncE DPLL state Maciej Machnikowski
2021-12-01 18:02 ` [PATCH v4 net-next 4/4] ice: add support for SyncE recovered clocks Maciej Machnikowski
2021-12-02 1:56 ` Jakub Kicinski
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