[PATCH net-next 0/2] Fix RGMII delays for 88E1118

[PATCH net-next 0/2] Fix RGMII delays for 88E1118

[Russell King (Oracle)]

Hi,

This series fixes the RGMII delays for 88E1118 Marvell PHYs, after a
report by Corentin Labbe that the Marvell driver fails to work.

Patch 1 cleans up the paged register accesses in m88e1118_config_init()
and patch 2 adds the RGMII delay configuration.

This comes with an element of risk as existing DT may need to be fixed
for this in a similar way as we have done in the recent past for other
PHY drivers that have misinterpreted the RGMII interface modes.

 drivers/net/phy/marvell.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

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[PATCH net-next 1/2] net: phy: marvell: use phy_write_paged() to set MSCR

[Russell King (Oracle)]

Use phy_write_paged() in m88e1118_config_init() to set the MSCR value.
We leave the other paged write for the LEDs in case the DT register
parsing is relying on this page.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
 drivers/net/phy/marvell.c | 22 ++++++++--------------
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 4fcfca4e1702..64e7874c95f4 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -1225,28 +1225,22 @@ static int m88e1118_config_aneg(struct phy_device *phydev)
 
 static int m88e1118_config_init(struct phy_device *phydev)
 {
+	u16 leds;
 	int err;
 
-	/* Change address */
-	err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
-	if (err < 0)
-		return err;
-
 	/* Enable 1000 Mbit */
-	err = phy_write(phydev, 0x15, 0x1070);
-	if (err < 0)
-		return err;
-
-	/* Change address */
-	err = marvell_set_page(phydev, MII_MARVELL_LED_PAGE);
+	err = phy_write_paged(phydev, MII_MARVELL_MSCR_PAGE,
+			      MII_88E1121_PHY_MSCR_REG, 0x1070);
 	if (err < 0)
 		return err;
 
 	/* Adjust LED Control */
 	if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
-		err = phy_write(phydev, 0x10, 0x1100);
+		leds = 0x1100;
 	else
-		err = phy_write(phydev, 0x10, 0x021e);
+		leds = 0x021e;
+
+	err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, 0x10, leds);
 	if (err < 0)
 		return err;
 
@@ -1254,7 +1248,7 @@ static int m88e1118_config_init(struct phy_device *phydev)
 	if (err < 0)
 		return err;
 
-	/* Reset address */
+	/* Reset page register */
 	err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
 	if (err < 0)
 		return err;
-- 
2.30.2

Re: [PATCH net-next 1/2] net: phy: marvell: use phy_write_paged() to set MSCR

[Andrew Lunn]

On Tue, Jan 04, 2022 at 04:38:13PM +0000, Russell King (Oracle) wrote:
> Use phy_write_paged() in m88e1118_config_init() to set the MSCR value.
> We leave the other paged write for the LEDs in case the DT register
> parsing is relying on this page.
> 
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next 1/2] net: phy: marvell: use phy_write_paged() to set MSCR

[Corentin Labbe]

Le Tue, Jan 04, 2022 at 04:38:13PM +0000, Russell King (Oracle) a écrit :
> Use phy_write_paged() in m88e1118_config_init() to set the MSCR value.
> We leave the other paged write for the LEDs in case the DT register
> parsing is relying on this page.
> 
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
> ---
>  drivers/net/phy/marvell.c | 22 ++++++++--------------
>  1 file changed, 8 insertions(+), 14 deletions(-)
> 

Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com>

Thanks!

[PATCH net-next 2/2] net: phy: marvell: configure RGMII delays for 88E1118

[Russell King (Oracle)]

Corentin Labbe reports that the SSI 1328 does not work when allowing
the PHY to operate at gigabit speeds, but does work with the generic
PHY driver.

This appears to be because m88e1118_config_init() writes a fixed value
to the MSCR register, claiming that this is to enable 1G speeds.
However, this always sets bits 4 and 5, enabling RGMII transmit and
receive delays. The suspicion is that the original board this was
added for required the delays to make 1G speeds work.

Add the necessary configuration for RGMII delays for the 88E1118 to
bring this into line with the requirements for RGMII support, and thus
make the SSI 1328 work.

Corentin Labbe has tested this on gemini-ssi1328 and gemini-ns2502.

Reported-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
 drivers/net/phy/marvell.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 64e7874c95f4..739859c0dfb1 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -1234,6 +1234,12 @@ static int m88e1118_config_init(struct phy_device *phydev)
 	if (err < 0)
 		return err;
 
+	if (phy_interface_is_rgmii(phydev)) {
+		err = m88e1121_config_aneg_rgmii_delays(phydev);
+		if (err < 0)
+			return err;
+	}
+
 	/* Adjust LED Control */
 	if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
 		leds = 0x1100;
-- 
2.30.2

Re: [PATCH net-next 2/2] net: phy: marvell: configure RGMII delays for 88E1118

[Andrew Lunn]

On Tue, Jan 04, 2022 at 04:38:19PM +0000, Russell King (Oracle) wrote:
> Corentin Labbe reports that the SSI 1328 does not work when allowing
> the PHY to operate at gigabit speeds, but does work with the generic
> PHY driver.
> 
> This appears to be because m88e1118_config_init() writes a fixed value
> to the MSCR register, claiming that this is to enable 1G speeds.
> However, this always sets bits 4 and 5, enabling RGMII transmit and
> receive delays. The suspicion is that the original board this was
> added for required the delays to make 1G speeds work.
> 
> Add the necessary configuration for RGMII delays for the 88E1118 to
> bring this into line with the requirements for RGMII support, and thus
> make the SSI 1328 work.
> 
> Corentin Labbe has tested this on gemini-ssi1328 and gemini-ns2502.
> 
> Reported-by: Corentin Labbe <clabbe.montjoie@gmail.com>
> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next 0/2] Fix RGMII delays for 88E1118

[patchwork-bot+netdevbpf]

Hello:

This series was applied to netdev/net-next.git (master)
by Jakub Kicinski <kuba@kernel.org>:

On Tue, 4 Jan 2022 16:37:21 +0000 you wrote:
> Hi,
> 
> This series fixes the RGMII delays for 88E1118 Marvell PHYs, after a
> report by Corentin Labbe that the Marvell driver fails to work.
> 
> Patch 1 cleans up the paged register accesses in m88e1118_config_init()
> and patch 2 adds the RGMII delay configuration.
> 
> [...]

Here is the summary with links:
  - [net-next,1/2] net: phy: marvell: use phy_write_paged() to set MSCR
    https://git.kernel.org/netdev/net-next/c/5b8f970309dd
  - [net-next,2/2] net: phy: marvell: configure RGMII delays for 88E1118
    https://git.kernel.org/netdev/net-next/c/f22725c95ece

You are awesome, thank you!
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