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Date:   Wed, 2 Mar 2022 04:22:52 +0100
From:   Andrew Lunn <andrew@lunn.ch>
To:     Arun Ramadoss <arun.ramadoss@microchip.com>
Cc:     netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
        Heiner Kallweit <hkallweit1@gmail.com>,
        Russell King <linux@armlinux.org.uk>,
        Jakub Kicinski <kuba@kernel.org>,
        "David S . Miller" <davem@davemloft.net>
Subject: Re: [RFC PATCH net-next 3/4] net: phy: added the LAN937x phy support
Message-ID: <Yh7jDF5CITerGkfF@lunn.ch>
References: <20220228140510.20883-1-arun.ramadoss@microchip.com>
 <20220228140510.20883-4-arun.ramadoss@microchip.com>
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On Mon, Feb 28, 2022 at 07:35:09PM +0530, Arun Ramadoss wrote:
> LAN937x T1 Phy is based on LAN87xx Phy, so reusing the init script of
> the Lan87xx. There is a workaround in accessing the DSP bank register
> for Lan937x Phy. Whenever there is a bank switch to DSP registers, then
> we need a dummy read access before proceeding to the actual register
> access.
> 
> Signed-off-by: Prasanna Vengateshan <prasanna.vengateshan@microchip.com>
> Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> ---
>  drivers/net/phy/microchip_t1.c | 47 +++++++++++++++++++++++++++++++---
>  1 file changed, 44 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/phy/microchip_t1.c b/drivers/net/phy/microchip_t1.c
> index 33325e5bd884..634a1423182a 100644
> --- a/drivers/net/phy/microchip_t1.c
> +++ b/drivers/net/phy/microchip_t1.c
> @@ -10,6 +10,7 @@
>  #include <linux/ethtool_netlink.h>
>  
>  #define LAN87XX_PHY_ID			0x0007c150
> +#define LAN937X_T1_PHY_ID		0x0007c181

I guess the last 1 is meaningless, given the mask?

  Andrew