From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDE10C433FE for ; Tue, 22 Mar 2022 00:47:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234435AbiCVAsh (ORCPT ); Mon, 21 Mar 2022 20:48:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234341AbiCVAsf (ORCPT ); Mon, 21 Mar 2022 20:48:35 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBBFC1C938; Mon, 21 Mar 2022 17:47:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=59s+ADf1BnOZDJpEUupH6dQ+wtfTBnaf9al8HVTZ3Pk=; b=sWnwNtXA41fFknrAgiMjxnMxG4 J8sDqtL6TLufFRtnDxa11WAAm3S9HlxvfPqfwN5TuVxw1CoS69V+lUqydICnWGJrcPWIzzh6YmlKF N+tXk/M7uguexV5LQeBfTS8Wo9k3HZ4UaeXbCa0EdMSNZuyta8K1qagkfRuvqKj01Pms=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1nWSGn-00C2mG-Nz; Tue, 22 Mar 2022 01:21:05 +0100 Date: Tue, 22 Mar 2022 01:21:05 +0100 From: Andrew Lunn To: Rob Herring Cc: Radhey Shyam Pandey , Andy Chiu , "robert.hancock@calian.com" , Michal Simek , "davem@davemloft.net" , "kuba@kernel.org" , "pabeni@redhat.com" , "linux@armlinux.org.uk" , "netdev@vger.kernel.org" , "devicetree@vger.kernel.org" , Greentime Hu , Harini Katakam Subject: Re: [PATCH v4 3/4] dt-bindings: net: xilinx_axienet: add pcs-handle attribute Message-ID: References: <20220321152515.287119-1-andy.chiu@sifive.com> <20220321152515.287119-3-andy.chiu@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org > > The use case is generic i.e. require separate handle to internal SGMII > > and external Phy so would prefer this new DT convention is > > standardized or we discuss possible approaches on how to handle > > both phys and not add it as vendor specific property in the first > > place. > > IMO, you should use 'phys' for the internal PCS phy. That's aligned with > other uses like PCIe, SATA, etc. (there is phy h/w that will do PCS, > PCIe, SATA). 'phy-handle' is for the ethernet PHY. We need to be careful here, because the PCS can have a well defined set of registers accessible over MDIO. Generic PHY has no infrastructure for that, it is all inside phylink which implements the pcs registers which are part of 802.3. I also wonder if a PCS might actually have a generic PHY embedded in it to provide its lower interface? Andrew