Re: [PATCH v4 3/4] dt-bindings: net: xilinx_axienet: add pcs-handle attribute

[Rob Herring <robh@kernel.org>]

On Tue, Mar 22, 2022 at 01:21:05AM +0100, Andrew Lunn wrote:
> > > The use case is generic i.e. require separate handle to internal SGMII
> > > and external Phy so would prefer this new DT convention is 
> > > standardized or we discuss possible approaches on how to handle
> > > both phys and not add it as vendor specific property in the first 
> > > place.
> > 
> > IMO, you should use 'phys' for the internal PCS phy. That's aligned with 
> > other uses like PCIe, SATA, etc. (there is phy h/w that will do PCS, 
> > PCIe, SATA). 'phy-handle' is for the ethernet PHY.
> 
> We need to be careful here, because the PCS can have a well defined
> set of registers accessible over MDIO. Generic PHY has no
> infrastructure for that, it is all inside phylink which implements the
> pcs registers which are part of 802.3.

Using the phy binding doesn't mean you have to use the kernel's 'generic 
PHY' subsytem.

But if there's a need to do something different then propose something 
that handles the complex cases.

> 
> I also wonder if a PCS might actually have a generic PHY embedded in
> it to provide its lower interface?

That's just looking at a single PCS/PHY block the other way around. 
PCS is part of the PHY or the PHY is part of PCS? I don't think that 
matters too much. I think the 2 cases would be it's all 1 block or 2 
blocks.

Rob