From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6AA0C433EF for ; Thu, 28 Apr 2022 23:17:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353224AbiD1XUa (ORCPT ); Thu, 28 Apr 2022 19:20:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229842AbiD1XU3 (ORCPT ); Thu, 28 Apr 2022 19:20:29 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0A2840935; Thu, 28 Apr 2022 16:17:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=810WVWqP/hZF1NMKzf5cATOlxW75bWI6UJtYB2eczzg=; b=4AQnes1B0vsSlqlcfMiO57RV7j QvPbQxQQwd+ZompegfVs1Gr6w3fgp+yav0rRZq2aW03tK1pIUxmZfUjxX5UzP44Tq1VSajsjnrKRx TIbb/ThR0jVVGBb0Uo/UfbNKtHXiemu2x6zBcYuCGpCBJU7x3NUEVzEOEDEgJeGOHScs=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1nkDNn-000OKv-Bo; Fri, 29 Apr 2022 01:17:11 +0200 Date: Fri, 29 Apr 2022 01:17:11 +0200 From: Andrew Lunn To: Nathan Rossi Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Paolo Abeni Subject: Re: [PATCH v2] net: dsa: mv88e6xxx: Single chip mode detection for MV88E6*41 Message-ID: References: <20220427130928.540007-1-nathan@nathanrossi.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220427130928.540007-1-nathan@nathanrossi.com> Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Wed, Apr 27, 2022 at 01:09:28PM +0000, Nathan Rossi wrote: > The mv88e6xxx driver expects switches that are configured in single chip > addressing mode to have the MDIO address configured as 0. This is due to > the switch ADDR pins representing the single chip addressing mode as 0. > However depending on the device (e.g. MV88E6*41) the switch does not > respond on address 0 or any other address below 16 (the first port > address) in single chip addressing mode. This allows for other devices > to be on the same shared MDIO bus despite the switch being in single > chip addressing mode. > > When using a switch that works this way it is not possible to configure > switch driver as single chip addressing via device tree, along with > another MDIO device on the same bus with address 0, as both devices > would have the same address of 0 resulting in mdiobus_register_device > -EBUSY errors for one of the devices with address 0. > > In order to support this configuration the switch node can have its MDIO > address configured as 16 (the first address that the device responds > to). During initialization the driver will treat this address similar to > how address 0 is, however because this address is also a valid > multi-chip address (in certain switch models, but not all) the driver > will configure the SMI in single chip addressing mode and attempt to > detect the switch model. If the device is configured in single chip > addressing mode this will succeed and the initialization process can > continue. If it fails to detect a valid model this is because the switch > model register is not a valid register when in multi-chip mode, it will > then fall back to the existing SMI initialization process using the MDIO > address as the multi-chip mode address. > > This detection method is safe if the device is in either mode because > the single chip addressing mode read is a direct SMI/MDIO read operation > and has no side effects compared to the SMI writes required for the > multi-chip addressing mode. > > In order to implement this change, the reset gpio configuration is moved > to occur before any SMI initialization. This ensures that the device has > the same/correct reset gpio state for both mv88e6xxx_smi_init calls. > > Signed-off-by: Nathan Rossi Reviewed-by: Andrew Lunn Andrew