From: Andrew Lunn <andrew@lunn.ch>
To: Nate Drude <nate.d@variscite.com>
Cc: netdev@vger.kernel.org, michael.hennerich@analog.com,
eran.m@variscite.com
Subject: Re: [PATCH 1/2] dt-bindings: net: adin: document adi,clk_rcvr_125_en property
Date: Sat, 30 Apr 2022 00:37:45 +0200 [thread overview]
Message-ID: <YmxouZJPpdCXhtLJ@lunn.ch> (raw)
In-Reply-To: <20220429184432.962738-1-nate.d@variscite.com>
On Fri, Apr 29, 2022 at 01:44:31PM -0500, Nate Drude wrote:
> Document device tree property to set GE_CLK_RCVR_125_EN (bit 5 of GE_CLK_CFG),
> causing the 125 MHz PHY recovered clock (or PLL clock) to be driven at
> the GP_CLK pin.
Hi Nate
Have you seen:
https://lore.kernel.org/netdev/20220419102709.26432-1-josua@solid-run.com/
Andrew
next prev parent reply other threads:[~2022-04-29 22:37 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-29 18:44 [PATCH 1/2] dt-bindings: net: adin: document adi,clk_rcvr_125_en property Nate Drude
2022-04-29 18:44 ` [PATCH 2/2] net: phy: adin: add " Nate Drude
2022-05-02 22:03 ` Jakub Kicinski
2022-04-29 22:37 ` Andrew Lunn [this message]
2022-05-02 9:03 ` [PATCH 1/2] dt-bindings: net: adin: document " Paolo Abeni
2022-05-03 11:50 ` Krzysztof Kozlowski
2022-05-05 12:40 ` Nate Drude
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