From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4472C19F2B for ; Sat, 30 Jul 2022 03:55:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239832AbiG3DzY (ORCPT ); Fri, 29 Jul 2022 23:55:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230251AbiG3DzX (ORCPT ); Fri, 29 Jul 2022 23:55:23 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF78814D2E; Fri, 29 Jul 2022 20:55:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=gjwGvuIYlf7YURpygwYL3YCCMDNSe/5O6oVE1XLk23k=; b=ZYUfs1+1e4ls90l1z7FI1IjfsV y6HXSTTXO7KiFdvT1ncL/nrAV0qzX9copWCDrD4jsLPOBJ0DXiSmDKjs2GmgTEiDOKhAxFHVYTPW4 u7RAi7MtzrxbdSacHnD7VIKCqzLMo2j5I/3An1YCyxid+o0Oo7feza5JE8fVY3ffckOc=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1oHdZN-00BzR1-Tv; Sat, 30 Jul 2022 05:55:17 +0200 Date: Sat, 30 Jul 2022 05:55:17 +0200 From: Andrew Lunn To: Maxime Chevallier Cc: davem@davemloft.net, Rob Herring , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, thomas.petazzoni@bootlin.com, Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-kernel@lists.infradead.org, Richard Cochran , Horatiu.Vultur@microchip.com, Allan.Nielsen@microchip.com, UNGLinuxDriver@microchip.com Subject: Re: [PATCH net-next v3 1/4] net: phy: Introduce QUSGMII PHY mode Message-ID: References: <20220729153356.581444-1-maxime.chevallier@bootlin.com> <20220729153356.581444-2-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220729153356.581444-2-maxime.chevallier@bootlin.com> Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Fri, Jul 29, 2022 at 05:33:53PM +0200, Maxime Chevallier wrote: > The QUSGMII mode is a derivative of Cisco's USXGMII standard. This > standard is pretty similar to SGMII, but allows for faster speeds, and > has the build-in bits for Quad and Octa variants (like QSGMII). > > The main difference with SGMII/QSGMII is that USXGMII/QUSGMII re-uses > the preamble to carry various information, named 'Extensions'. > > As of today, the USXGMII standard only mentions the "PCH" extension, > which is used to convey timestamps, allowing in-band signaling of PTP > timestamps without having to modify the frame itself. > > This commit adds support for that mode. When no extension is in use, it > behaves exactly like QSGMII, although it's not compatible with QSGMII. > > Signed-off-by: Maxime Chevallier Reviewed-by: Andrew Lunn Andrew