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Tue, 03 Dec 2024 18:27:36 -0800 (PST) Received: from fan ([2601:646:8f03:9fee:204:6b61:1fa:ccc8]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72541770786sm11189074b3a.79.2024.12.03.18.27.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 18:27:35 -0800 (PST) From: Fan Ni X-Google-Original-From: Fan Ni Date: Tue, 3 Dec 2024 18:27:33 -0800 To: alejandro.lucero-palau@amd.com Cc: linux-cxl@vger.kernel.org, netdev@vger.kernel.org, dan.j.williams@intel.com, martin.habets@xilinx.com, edward.cree@amd.com, davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com, edumazet@google.com, dave.jiang@intel.com, Alejandro Lucero Subject: Re: [PATCH v6 06/28] cxl: add function for type2 cxl regs setup Message-ID: References: <20241202171222.62595-1-alejandro.lucero-palau@amd.com> <20241202171222.62595-7-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241202171222.62595-7-alejandro.lucero-palau@amd.com> On Mon, Dec 02, 2024 at 05:12:00PM +0000, alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero > > Create a new function for a type2 device initialising > cxl_dev_state struct regarding cxl regs setup and mapping. > > Signed-off-by: Alejandro Lucero > Reviewed-by: Dave Jiang > --- Reviewed-by: Fan Ni > drivers/cxl/core/pci.c | 47 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index 378ef2dfb15f..95191dff4dc9 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -1096,6 +1096,53 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > } > EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL); > > +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, > + struct cxl_dev_state *cxlds) > +{ > + struct cxl_register_map map; > + int rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, > + cxlds->capabilities); > + /* > + * This call returning a non-zero value is not considered an error since > + * these regs are not mandatory for Type2. If they do exist then mapping > + * them should not fail. > + */ > + if (rc) > + return 0; > + > + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); > +} > + > +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) > +{ > + int rc; > + > + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); > + if (rc) > + return rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > + &cxlds->reg_map, cxlds->capabilities); > + if (rc) { > + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); > + return rc; > + } > + > + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) > + return rc; > + > + rc = cxl_map_component_regs(&cxlds->reg_map, > + &cxlds->regs.component, > + BIT(CXL_CM_CAP_CAP_ID_RAS)); > + if (rc) > + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); > + > + return rc; > +} > +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, CXL); > + > int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c) > { > int speed, bw; > -- > 2.17.1 > -- Fan Ni