From: Michal Swiatkowski <michal.swiatkowski@linux.intel.com>
To: Michael Chan <michael.chan@broadcom.com>
Cc: davem@davemloft.net, netdev@vger.kernel.org, edumazet@google.com,
kuba@kernel.org, pabeni@redhat.com, andrew+netdev@lunn.ch,
pavan.chebbi@broadcom.com, andrew.gospodarek@broadcom.com,
somnath.kotur@broadcom.com,
Ajit Khaparde <ajit.khaparde@broadcom.com>
Subject: Re: [PATCH net-next 02/10] bnxt_en Refactor completion ring allocation logic for P5_PLUS chips
Date: Mon, 13 Jan 2025 08:59:08 +0100 [thread overview]
Message-ID: <Z4THzLTGKCgp/SUQ@mev-dev.igk.intel.com> (raw)
In-Reply-To: <20250113063927.4017173-3-michael.chan@broadcom.com>
On Sun, Jan 12, 2025 at 10:39:19PM -0800, Michael Chan wrote:
> Add a new bnxt_hwrm_cp_ring_alloc_p5() function to handle allocating
> one completion ring on P5_PLUS chips. This simplifies the existing code
> and will be useful later in the series.
>
> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
> Signed-off-by: Michael Chan <michael.chan@broadcom.com>
> ---
> drivers/net/ethernet/broadcom/bnxt/bnxt.c | 44 +++++++++++------------
> 1 file changed, 21 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
> index 8527788bed91..d364a707664b 100644
> --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
> +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
> @@ -7172,6 +7172,25 @@ static int bnxt_hwrm_rx_agg_ring_alloc(struct bnxt *bp,
> return 0;
> }
>
> +static int bnxt_hwrm_cp_ring_alloc_p5(struct bnxt *bp,
> + struct bnxt_cp_ring_info *cpr)
> +{
> + struct bnxt_napi *bnapi = cpr->bnapi;
> + u32 type = HWRM_RING_ALLOC_CMPL;
Nit, can be const
> + struct bnxt_ring_struct *ring;
> + u32 map_idx = bnapi->index;
> + int rc;
> +
> + ring = &cpr->cp_ring_struct;
> + ring->handle = BNXT_SET_NQ_HDL(cpr);
> + rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
> + if (rc)
> + return rc;
> + bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
> + bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
> + return 0;
> +}
> +
> static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
> {
> bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS);
> @@ -7215,19 +7234,9 @@ static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
> u32 map_idx;
>
> if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
> - struct bnxt_cp_ring_info *cpr2 = txr->tx_cpr;
> - struct bnxt_napi *bnapi = txr->bnapi;
> - u32 type2 = HWRM_RING_ALLOC_CMPL;
> -
> - ring = &cpr2->cp_ring_struct;
> - ring->handle = BNXT_SET_NQ_HDL(cpr2);
> - map_idx = bnapi->index;
> - rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
> + rc = bnxt_hwrm_cp_ring_alloc_p5(bp, txr->tx_cpr);
> if (rc)
> goto err_out;
> - bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
> - ring->fw_ring_id);
> - bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
> }
> ring = &txr->tx_ring_struct;
> map_idx = i;
> @@ -7247,20 +7256,9 @@ static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
> if (!agg_rings)
> bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
> if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
> - struct bnxt_cp_ring_info *cpr2 = rxr->rx_cpr;
> - struct bnxt_napi *bnapi = rxr->bnapi;
> - u32 type2 = HWRM_RING_ALLOC_CMPL;
> - struct bnxt_ring_struct *ring;
> - u32 map_idx = bnapi->index;
> -
> - ring = &cpr2->cp_ring_struct;
> - ring->handle = BNXT_SET_NQ_HDL(cpr2);
> - rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
> + rc = bnxt_hwrm_cp_ring_alloc_p5(bp, rxr->rx_cpr);
> if (rc)
> goto err_out;
> - bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
> - ring->fw_ring_id);
> - bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
> }
> }
>
> --
> 2.30.1
Nice simplification
Reviewed-by: Michal Swiatkowski <michal.swiatkowski@linux.intel.com>
next prev parent reply other threads:[~2025-01-13 8:02 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-13 6:39 [PATCH net-next 00/10] bnxt_en: Add NPAR 1.2 and TPH support Michael Chan
2025-01-13 6:39 ` [PATCH net-next 01/10] bnxt_en: Set NAPR 1.2 support when registering with firmware Michael Chan
2025-01-13 7:56 ` Michal Swiatkowski
2025-01-13 6:39 ` [PATCH net-next 02/10] bnxt_en Refactor completion ring allocation logic for P5_PLUS chips Michael Chan
2025-01-13 7:59 ` Michal Swiatkowski [this message]
2025-01-13 6:39 ` [PATCH net-next 03/10] bnxt_en: Refactor TX ring allocation logic Michael Chan
2025-01-13 8:02 ` Michal Swiatkowski
2025-01-13 6:39 ` [PATCH net-next 04/10] bnxt_en: Refactor completion ring free routine Michael Chan
2025-01-13 8:06 ` Michal Swiatkowski
2025-01-13 6:39 ` [PATCH net-next 05/10] bnxt_en: Refactor bnxt_free_tx_rings() to free per Tx ring Michael Chan
2025-01-13 8:17 ` Michal Swiatkowski
2025-01-13 6:39 ` [PATCH net-next 06/10] bnxt_en: Refactor RX/RX AGG ring parameters setup for P5_PLUS Michael Chan
2025-01-13 8:27 ` Michal Swiatkowski
2025-01-13 6:39 ` [PATCH net-next 07/10] bnxt_en: Pass NQ ID to the FW when allocating RX/RX AGG rings Michael Chan
2025-01-13 8:29 ` Michal Swiatkowski
2025-01-13 6:39 ` [PATCH net-next 08/10] bnxt_en: Reallocate Rx completion ring for TPH support Michael Chan
2025-01-13 8:35 ` Michal Swiatkowski
2025-01-14 21:42 ` Michael Chan
2025-01-15 5:58 ` Michal Swiatkowski
2025-01-13 6:39 ` [PATCH net-next 09/10] bnxt_en: Extend queue stop/start for Tx rings Michael Chan
2025-01-13 8:40 ` Michal Swiatkowski
2025-01-14 2:05 ` Somnath Kotur
2025-01-15 1:29 ` Michael Chan
2025-01-13 16:01 ` Bjorn Helgaas
2025-01-14 4:57 ` Somnath Kotur
2025-01-14 8:48 ` kernel test robot
2025-01-14 11:23 ` kernel test robot
2025-01-13 6:39 ` [PATCH net-next 10/10] bnxt_en: Add TPH support in BNXT driver Michael Chan
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