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From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Tristram.Ha@microchip.com
Cc: olteanv@gmail.com, Woojung.Huh@microchip.com, andrew@lunn.ch,
	hkallweit1@gmail.com, Jose.Abreu@synopsys.com,
	maxime.chevallier@bootlin.com, davem@davemloft.net,
	edumazet@google.com, kuba@kernel.org, pabeni@redhat.com,
	UNGLinuxDriver@microchip.com, netdev@vger.kernel.org,
	linux-kernel@vger.kernel.org, Sadhan.Rudresh@synopsys.com,
	Siddhant.Kumar@synopsys.com
Subject: Re: [WARNING: ATTACHMENT UNSCANNED]Re: [WARNING: ATTACHMENT UNSCANNED]Re: [PATCH RFC net-next 1/2] net: pcs: xpcs: Add special code to operate in Microchip KSZ9477 switch
Date: Sat, 1 Feb 2025 09:20:09 +0000	[thread overview]
Message-ID: <Z53nSexf2BaUQiCY@shell.armlinux.org.uk> (raw)
In-Reply-To: <DM3PR11MB87369DE499570C4D4A6E3C9FECEB2@DM3PR11MB8736.namprd11.prod.outlook.com>

On Sat, Feb 01, 2025 at 01:12:00AM +0000, Tristram.Ha@microchip.com wrote:
> > On Fri, Jan 31, 2025 at 02:36:49PM +0000, Jose Abreu wrote:
> > > From: Russell King (Oracle) <linux@armlinux.org.uk>
> > > Date: Thu, Jan 30, 2025 at 11:02:00
> > >
> > > > Would it be safe to set these two bits with newer XPCS hardware when
> > > > programming it for 1000base-X mode, even though documentation e.g.
> > > > for SJA1105 suggests that these bits do not apply when operating in
> > > > 1000base-X mode?
> > >
> > > It's hard to provide a clear answer because our products can all be modified
> > > by final customer. I hope this snippet below can help:
> > >
> > > "Nothing has changed in "AN control register" ever since at least for a decade.
> > > Having said that, bit[4] and bit[3] are valid for SGMII mode and not valid
> > > for 1000BASE-X mode (I don't know why customer says 'serdes' mode.
> > > There is no such mode in ethernet standard). So, customer shall
> > > leave this bits at default value of 0.  Even if they set to 1, there is no
> > > impact (as those bits are not used in 1000BASE-X mode)."
> > 
> > Thanks for the reply Jose, that's useful.
> > 
> > Tristram, I think you need to talk to your hardware people to find out
> > where this requirement to set these two bits comes from as it seems it
> > isn't a property that comes from Synopsys' IP (I suppose unless your
> > IP is older than ten years.)
> > 
> > That said, Jose's response indicates that we can set these two bits
> > with impunity provided another of Synopsys's customers hasn't modified
> > their integration of XPCS to require these bits to be set to zero. So,
> > while I think we can do that unconditionally (as per the patch
> > attached) I think we need a clearer comment to state why it's being
> > done (and I probably need to now modify the commit message - this was
> > created before Jose's reply.)
> > 
> > So, I think given the last two patches I've sent, I believe I've
> > covered both of the issues that you have with XPCS:
> > 
> > 1) the need to set bits 4 and 3 in AN control for 1000base-X in KSZ9477
> >    (subject to a better commit message and code comment, which will be
> >     dependent on your research as to where this requirement has come
> >     from.)
> > 
> > 2) the lack of MAC_AUTO_SW support in KSZ9477 which can be enabled by
> >    writing DW_XPCS_SGMII_MODE_MAC_MANUAL to xpcs->sgmii_mode.
> > 
> > We now need to work out a way to identify this older IP. I think for
> > (2) we could potentially do something like (error handling omitted for
> > clarity):
> > 
> >         if (xpcs->sgmii_mode == DW_XPCS_SGMII_MODE_MAC_AUTO) {
> >                 xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL,
> >                             DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW,
> >                             DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW);
> > 
> >                 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
> > 
> >                 /* If MAC_AUTO_SW doesn't retain the MAC_AUTO_SW bit, then the
> >                  * XPCS implementation does not support this feature, and we
> >                  * have to manually configure the BMCR for the link parameters.
> >                  */
> >                 if (ret >= 0 && !(ret & DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW))
> >                         xpcs->sgmii_mode = DW_XPCS_SGMII_MODE_MAC_MANUAL;
> >         }
> 
> The IP document says version 3.10a and has date August 2013.
> 
> Indeed it does not make sense to use SGMII_LINK_STS and
> TX_CONFIG_PHY_SIDE_SGMII in 1000BASEX mode.
> 
> My thinking is there may be a hardware bug to prevent 1000BASEX mode to
> work when auto-negotiation is enabled.  And somehow setting those bits
> workaround that, and those bits have different meanings.
> 
> In order not to use those bits auto-negotiation needs to be disabled.  Is
> there a way to do that in normal driver activation?

You do not want to do that. While you may negotiate with a PHY using
1000base-X that has "bypass" mode enabled, anything that doesn't have
a "bypass" mode or has it disabled won't work.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

  reply	other threads:[~2025-02-01  9:20 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-28  3:32 [PATCH RFC net-next 0/2] Add SGMII port support to KSZ9477 switch Tristram.Ha
2025-01-28  3:32 ` [PATCH RFC net-next 1/2] net: pcs: xpcs: Add special code to operate in Microchip " Tristram.Ha
2025-01-28  9:24   ` Russell King (Oracle)
2025-01-28 10:21     ` Vladimir Oltean
2025-01-28 12:33       ` Russell King (Oracle)
2025-01-28 15:23         ` Vladimir Oltean
2025-01-28 16:32           ` Russell King (Oracle)
2025-01-28 18:26             ` Vladimir Oltean
2025-01-29  0:31           ` Tristram.Ha
2025-01-29 21:12             ` Vladimir Oltean
2025-01-29 22:05               ` Russell King (Oracle)
2025-01-29 23:05                 ` Vladimir Oltean
2025-01-30 12:44                   ` Russell King (Oracle)
2025-01-30 17:42                     ` Russell King (Oracle)
2025-01-30  4:50                 ` [WARNING: ATTACHMENT UNSCANNED]Re: " Tristram.Ha
2025-01-30 10:02                   ` Vladimir Oltean
2025-01-30 11:02                     ` Russell King (Oracle)
2025-01-30 11:20                       ` Jose Abreu
2025-01-31 14:36                       ` Jose Abreu
2025-01-31 15:49                         ` Russell King (Oracle)
2025-02-01  1:12                           ` [WARNING: ATTACHMENT UNSCANNED]Re: " Tristram.Ha
2025-02-01  9:20                             ` Russell King (Oracle) [this message]
2025-01-31  2:35                     ` Tristram.Ha
2025-01-30 10:15                   ` Russell King (Oracle)
2025-01-31  2:35                     ` Tristram.Ha
2025-01-31 13:35                       ` Andrew Lunn
2025-02-01  1:11                         ` Tristram.Ha
2025-01-30  4:50               ` Tristram.Ha
2025-01-30  9:59                 ` Russell King (Oracle)
2025-01-31  2:24                   ` Tristram.Ha
2025-01-31  9:43                     ` Russell King (Oracle)
2025-01-30 13:24                 ` Andrew Lunn
2025-01-31  2:21                   ` Tristram.Ha
2025-01-28 12:40       ` Russell King (Oracle)
2025-01-28 13:16   ` Andrew Lunn
2025-01-28 13:39     ` Russell King (Oracle)
2025-01-28 15:43   ` Vladimir Oltean
2025-01-29  0:31     ` Tristram.Ha
2025-01-28  3:32 ` [PATCH RFC net-next 2/2] net: dsa: microchip: Add SGMII port support to " Tristram.Ha
2025-01-28  9:38   ` Russell King (Oracle)

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