Re: [WARNING: ATTACHMENT UNSCANNED]Re: [PATCH RFC net-next 1/2] net: pcs: xpcs: Add special code to operate in Microchip KSZ9477 switch

["Russell King (Oracle)" <linux@armlinux.org.uk>]

On Thu, Jan 30, 2025 at 12:02:27PM +0200, Vladimir Oltean wrote:
> On Thu, Jan 30, 2025 at 04:50:18AM +0000, Tristram.Ha@microchip.com wrote:
> > This behavior only occurs in KSZ9477 with old IP and so may not reflect
> > in current specs.  If neg_mode can be set in certain way that disables
> > auto-negotiation in 1000BASEX mode but enables auto-negotiation in SGMII
> > mode then this setting is not required.
> 
> I see that the KSZ9477 documentation specifies that these bits "must be
> set to 1 when operating in SerDes mode", but gives no explanation whatsoever,
> and gives the description of the bits that matches what I see in the
> XPCS data book (which suggests they would not be needed for 1000Base-X,
> just for SGMII PHY role).

Hi Jose,

Can you help resolve this please?

Essentially, the KSZ9477 integration of the XPCS hardware used an old
version of XPCS (we don't know how old). The KSZ9477 documentation
states that in the AN control register (0x1f8001), buts 4 and 3 must
be set when operating in "SerDes" mode (aka 1000base-X).

See page 223 of
https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/KSZ9477S-Data-Sheet-DS00002392C.pdf

Is this something which the older XPCS hardware version requires?

Would it be safe to set these two bits with newer XPCS hardware when
programming it for 1000base-X mode, even though documentation e.g.
for SJA1105 suggests that these bits do not apply when operating in
1000base-X mode?

Many thanks.

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