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From: Richard Cochran <richardcochran@gmail.com>
To: Tianfei Zhang <tianfei.zhang@intel.com>
Cc: netdev@vger.kernel.org, linux-fpga@vger.kernel.org,
	ilpo.jarvinen@linux.intel.com, andriy.shevchenko@linux.intel.com,
	russell.h.weight@intel.com, matthew.gerlach@linux.intel.com,
	pierre-louis.bossart@linux.intel.com, vinicius.gomes@intel.com,
	Raghavendra Khadatare <raghavendrax.anand.khadatare@intel.com>
Subject: Re: [PATCH v1] ptp: add ToD device driver for Intel FPGA cards
Date: Mon, 13 Mar 2023 11:49:53 -0700	[thread overview]
Message-ID: <ZA9wUe33pMkhMu0e@hoboy.vegasvil.org> (raw)
In-Reply-To: <20230313030239.886816-1-tianfei.zhang@intel.com>

On Sun, Mar 12, 2023 at 11:02:39PM -0400, Tianfei Zhang wrote:


> +static int dfl_tod_probe(struct dfl_device *ddev)
> +{
> +	struct device *dev = &ddev->dev;
> +	struct dfl_tod *dt;
> +
> +	dt = devm_kzalloc(dev, sizeof(*dt), GFP_KERNEL);
> +	if (!dt)
> +		return -ENOMEM;
> +
> +	dt->tod_ctrl = devm_ioremap_resource(dev, &ddev->mmio_res);
> +	if (IS_ERR(dt->tod_ctrl))
> +		return PTR_ERR(dt->tod_ctrl);
> +
> +	dt->dev = dev;
> +	spin_lock_init(&dt->tod_lock);
> +	dev_set_drvdata(dev, dt);
> +
> +	dt->ptp_clock_ops = dfl_tod_clock_ops;
> +
> +	dt->ptp_clock = ptp_clock_register(&dt->ptp_clock_ops, dev);
> +	if (IS_ERR(dt->ptp_clock))
> +		return dev_err_probe(dt->dev, PTR_ERR(dt->ptp_clock),
> +				     "Unable to register PTP clock\n");

Need to handle NULL as well...

/**
 * ptp_clock_register() - register a PTP hardware clock driver
 *
 * @info:   Structure describing the new clock.
 * @parent: Pointer to the parent device of the new clock.
 *
 * Returns a valid pointer on success or PTR_ERR on failure.  If PHC
 * support is missing at the configuration level, this function
 * returns NULL, and drivers are expected to gracefully handle that
 * case separately.
 */

Thanks,
Richard


  parent reply	other threads:[~2023-03-13 18:50 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-13  3:02 [PATCH v1] ptp: add ToD device driver for Intel FPGA cards Tianfei Zhang
2023-03-13 17:50 ` Marco Pagani
2023-03-15  2:59   ` Zhang, Tianfei
2023-03-16 15:03     ` Zhang, Tianfei
2023-03-13 18:49 ` Richard Cochran [this message]
2023-03-14  7:16   ` Zhang, Tianfei
2023-03-14 20:01     ` Richard Cochran
2023-03-14 10:47   ` Andy Shevchenko
2023-03-14 19:46     ` Richard Cochran
2023-03-15 13:59       ` Andy Shevchenko
2023-03-15 14:37         ` Nicolas Pitre
2023-03-20 13:20           ` Andy Shevchenko
2023-03-20 13:43             ` Nicolas Pitre
2023-03-20 19:41               ` Richard Cochran
2023-03-20 20:53                 ` Nicolas Pitre
2023-03-21 13:02                   ` Andy Shevchenko
2023-03-21 14:28                     ` Zhang, Tianfei
2023-03-21 14:40                       ` Andy Shevchenko
2023-03-21 14:52                         ` Zhang, Tianfei
2023-03-22  4:17                           ` Richard Cochran

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