From: andy.shevchenko@gmail.com
To: Rohit Agarwal <quic_rohiagar@quicinc.com>
Cc: agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, linus.walleij@linaro.org,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
richardcochran@gmail.com, manivannan.sadhasivam@linaro.org,
linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
netdev@vger.kernel.org
Subject: Re: [PATCH v4 2/2] pinctrl: qcom: Add SDX75 pincontrol driver
Date: Wed, 26 Apr 2023 18:04:55 +0300 [thread overview]
Message-ID: <ZEk9lySMZcrRZYwX@surfacebook> (raw)
In-Reply-To: <1682327030-25535-3-git-send-email-quic_rohiagar@quicinc.com>
Mon, Apr 24, 2023 at 02:33:50PM +0530, Rohit Agarwal kirjoitti:
> Add initial Qualcomm SDX75 pinctrl driver to support pin configuration
> with pinctrl framework for SDX75 SoC.
> While at it, reordering the SDX65 entry.
...
> +#define FUNCTION(fname) \
> + [msm_mux_##fname] = { \
> + .name = #fname, \
> + .groups = fname##_groups, \
> + .ngroups = ARRAY_SIZE(fname##_groups), \
> + }
PINCTRL_PINFUNCTION() ?
...
> +static const struct of_device_id sdx75_pinctrl_of_match[] = {
> + {.compatible = "qcom,sdx75-tlmm", .data = &sdx75_pinctrl}, {},
One entry per line.
And drop comma in the terminator one.
> +};
No MODULE_DEVICE_TABLE()?
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2023-04-26 15:07 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-24 9:03 [PATCH v4 0/2] Add pinctrl support for SDX75 Rohit Agarwal
2023-04-24 9:03 ` [PATCH v4 1/2] dt-bindings: pinctrl: qcom: Add SDX75 pinctrl devicetree compatible Rohit Agarwal
2023-04-24 9:45 ` Krzysztof Kozlowski
2023-04-24 9:03 ` [PATCH v4 2/2] pinctrl: qcom: Add SDX75 pincontrol driver Rohit Agarwal
2023-04-26 15:04 ` andy.shevchenko [this message]
2023-04-26 15:18 ` Rohit Agarwal
2023-04-26 16:42 ` Andy Shevchenko
2023-04-27 8:53 ` Rohit Agarwal
2023-04-27 10:54 ` Andy Shevchenko
2023-04-27 11:07 ` Rohit Agarwal
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