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From: andy.shevchenko@gmail.com
To: Jiawen Wu <jiawenwu@trustnetic.com>
Cc: netdev@vger.kernel.org, jarkko.nikula@linux.intel.com,
	andriy.shevchenko@linux.intel.com,
	mika.westerberg@linux.intel.com, jsd@semihalf.com,
	Jose.Abreu@synopsys.com, andrew@lunn.ch, hkallweit1@gmail.com,
	linux@armlinux.org.uk, linux-i2c@vger.kernel.org,
	linux-gpio@vger.kernel.org, mengyuanlou@net-swift.com
Subject: Re: [PATCH net-next v7 6/9] net: txgbe: Support GPIO to SFP socket
Date: Thu, 11 May 2023 23:45:31 +0300	[thread overview]
Message-ID: <ZF1T62BnVFgR33w0@surfacebook> (raw)
In-Reply-To: <20230509022734.148970-7-jiawenwu@trustnetic.com>

Tue, May 09, 2023 at 10:27:31AM +0800, Jiawen Wu kirjoitti:
> Register GPIO chip and handle GPIO IRQ for SFP socket.

...

> +#include <linux/gpio/consumer.h>

What for?

> +#include <linux/gpio/machine.h>
> +#include <linux/gpio/driver.h>

...

> +static int txgbe_gpio_get(struct gpio_chip *chip, unsigned int offset)
> +{
> +	struct wx *wx = gpiochip_get_data(chip);
> +	struct txgbe *txgbe = wx->priv;
> +	int val;
> +
> +	val = rd32m(wx, WX_GPIO_EXT, BIT(offset));
> +
> +	txgbe->gpio_orig &= ~BIT(offset);
> +	txgbe->gpio_orig |= val;

This can use standard pattern in conjunction with simple rd32() call:

	txgbe->gpio_orig = (txgbe->gpio_orig & ~BIT(offset)) | (val & BIT(offset));

otherwise it's not immediately obvious that val can have only one bit set.

> +	return !!(val & BIT(offset));
> +}

...

> +static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset,
> +				    int val)
> +{
> +	struct wx *wx = gpiochip_get_data(chip);
> +	u32 mask;
> +
> +	mask = BIT(offset) | BIT(offset - 1);
> +	if (val)
> +		wr32m(wx, WX_GPIO_DR, mask, mask);
> +	else
> +		wr32m(wx, WX_GPIO_DR, mask, 0);
> +
> +	wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset));

Can you explain, what prevents to have this flow to be interleaved by other API
calls, like ->direction_in()? Didn't you missed proper locking schema?

> +	return 0;
> +}

...

> +	switch (type) {
> +	case IRQ_TYPE_EDGE_BOTH:
> +		level |= BIT(hwirq);
> +		break;
> +	case IRQ_TYPE_EDGE_RISING:
> +		level |= BIT(hwirq);
> +		polarity |= BIT(hwirq);
> +		break;
> +	case IRQ_TYPE_EDGE_FALLING:
> +		level |= BIT(hwirq);

> +		polarity &= ~BIT(hwirq);

This...

> +		break;
> +	case IRQ_TYPE_LEVEL_HIGH:
> +		level &= ~BIT(hwirq);

...and this can be done outside of the switch-case. Then you simply set certain
bits where it's needed.

> +		polarity |= BIT(hwirq);
> +		break;
> +	case IRQ_TYPE_LEVEL_LOW:
> +		level &= ~BIT(hwirq);
> +		polarity &= ~BIT(hwirq);
> +		break;

default?

> +	}

...

> +	/* workaround for hysteretic gpio interrupts */

GPIO

...

> +	gc->can_sleep = false;

Useless, kzalloc() already sets this to 0.

...

> +	girq->num_parents = 1;
> +	girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),

Use girq->num_parents instead of explicit 1 in this call.

> +				     GFP_KERNEL);

Also with 

	struct device *dev = &pdev->dev;

this (and others) can be modified as

	girq->parents = devm_kcalloc(dev, girq->num_parents, sizeof(*girq->parents),

> +	if (!girq->parents)
> +		return -ENOMEM;


...

> +#define TXGBE_PX_MISC_IEN_MASK ( \
> +				TXGBE_PX_MISC_ETH_LKDN | \
> +				TXGBE_PX_MISC_DEV_RST | \
> +				TXGBE_PX_MISC_ETH_EVENT | \
> +				TXGBE_PX_MISC_ETH_LK | \
> +				TXGBE_PX_MISC_ETH_AN | \
> +				TXGBE_PX_MISC_INT_ERR | \
> +				TXGBE_PX_MISC_GPIO)

Wouldn't be better

#define TXGBE_PX_MISC_IEN_MASK				  \
	(TXGBE_PX_MISC_ETH_LKDN | TXGBE_PX_MISC_ETH_LK |  \
	 TXGBE_PX_MISC_ETH_EVENT | TXGBE_PX_MISC_ETH_AN | \
	 TXGBE_PX_MISC_DEV_RST | TXGBE_PX_MISC_INT_ERR |  \
	 TXGBE_PX_MISC_GPIO)

?

-- 
With Best Regards,
Andy Shevchenko



  parent reply	other threads:[~2023-05-11 20:45 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-09  2:27 [PATCH net-next v7 0/9] TXGBE PHYLINK support Jiawen Wu
2023-05-09  2:27 ` [PATCH net-next v7 1/9] net: txgbe: Add software nodes to support phylink Jiawen Wu
2023-05-09 12:38   ` Piotr Raczynski
2023-05-09  2:27 ` [PATCH net-next v7 2/9] i2c: designware: Add driver support for Wangxun 10Gb NIC Jiawen Wu
2023-05-09 13:52   ` Piotr Raczynski
2023-05-10  6:43     ` Jiawen Wu
2023-05-10  7:47       ` andy.shevchenko
2023-05-10  8:00         ` Jiawen Wu
2023-05-09  2:27 ` [PATCH net-next v7 3/9] net: txgbe: Register fixed rate clock Jiawen Wu
2023-05-09 15:32   ` Simon Horman
2023-05-10  6:47     ` Jiawen Wu
2023-05-09  2:27 ` [PATCH net-next v7 4/9] net: txgbe: Register I2C platform device Jiawen Wu
2023-05-11 12:13   ` Andrew Lunn
2023-05-11 20:16   ` Piotr Raczynski
2023-05-09  2:27 ` [PATCH net-next v7 5/9] net: txgbe: Add SFP module identify Jiawen Wu
2023-05-11 12:13   ` Andrew Lunn
2023-05-11 20:18   ` Piotr Raczynski
2023-05-09  2:27 ` [PATCH net-next v7 6/9] net: txgbe: Support GPIO to SFP socket Jiawen Wu
2023-05-11 12:31   ` Andrew Lunn
2023-05-12  6:38     ` Jiawen Wu
2023-05-12 14:20       ` Andrew Lunn
2023-05-11 12:38   ` Andrew Lunn
2023-05-12  6:35     ` Jiawen Wu
2023-05-11 20:45   ` andy.shevchenko [this message]
2023-05-12  8:57     ` Jiawen Wu
2023-05-12  9:43       ` Andy Shevchenko
2023-05-12  9:32   ` Russell King (Oracle)
2023-05-12 10:46     ` Jiawen Wu
2023-05-09  2:27 ` [PATCH net-next v7 7/9] net: pcs: Add 10GBASE-R mode for Synopsys Designware XPCS Jiawen Wu
2023-05-11 12:40   ` Andrew Lunn
2023-05-09  2:27 ` [PATCH net-next v7 8/9] net: txgbe: Implement phylink pcs Jiawen Wu
2023-05-11 19:33   ` Andrew Lunn
2023-05-11 20:32   ` Piotr Raczynski
2023-05-12  9:22     ` Jiawen Wu
2023-05-09  2:27 ` [PATCH net-next v7 9/9] net: txgbe: Support phylink MAC layer Jiawen Wu

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