From: Daniel Golle <daniel@makrotopia.org>
To: Andrew Lunn <andrew@lunn.ch>
Cc: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Subject: Re: [PATCH 1/8] net: phy: realtek: rtl8221: allow to configure SERDES mode
Date: Thu, 11 May 2023 13:53:53 +0200 [thread overview]
Message-ID: <ZFzXPGeob0q4DTza@pidgin.makrotopia.org> (raw)
In-Reply-To: <81c3f04d-ec48-4ac0-ac16-b69dc6ae72e0@lunn.ch>
On Thu, May 11, 2023 at 02:41:07AM +0200, Andrew Lunn wrote:
> > +#define RTL8221B_MMD_SERDES_CTRL MDIO_MMD_VEND1
> > +#define RTL8221B_MMD_PHY_CTRL MDIO_MMD_VEND2
>
> I suggest you don't do this. Use MDIO_MMD_VEND[1|2] to make it clear
> these are vendor registers.
Ack, I will not introduce new macros to label them, but just use
MDIO_MMD_VEND1 and MDIO_MMD_VEND2 then.
>
> > + case RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII:
> > + case RTL8221B_SERDES_OPTION_MODE_2500BASEX:
> > + phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6a04, 0x0503);
> > + phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f10, 0xd455);
> > + phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f11, 0x8020);
> > + break;
> > + case RTL8221B_SERDES_OPTION_MODE_HISGMII_SGMII:
> > + case RTL8221B_SERDES_OPTION_MODE_HISGMII:
> > + phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6a04, 0x0503);
> > + phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f10, 0xd433);
> > + phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f11, 0x8020);
> > + break;
> > + }
>
> Is there anything in the datasheet to indicate register names and what
> the values mean? It would be good to replace these magic values with
> #defines.
Unfortunately they are only mentioned as magic values which have to be
written to magic registers also in the datasheet :(
next prev parent reply other threads:[~2023-05-11 11:55 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-10 22:53 [PATCH net-next 0/8] Improvements for RealTek 2.5G Ethernet PHYs Daniel Golle
2023-05-10 22:53 ` [PATCH net-next 1/8] net: phy: realtek: rtl8221: allow to configure SERDES mode Alexander Couzens
2023-05-10 22:56 ` [PATCH " Daniel Golle
2023-05-11 0:34 ` Andrew Lunn
2023-05-11 0:38 ` Andrew Lunn
2023-05-11 11:50 ` Daniel Golle
2023-05-11 0:41 ` Andrew Lunn
2023-05-11 11:53 ` Daniel Golle [this message]
2023-05-11 7:53 ` [PATCH net-next " Steen Hegelund
2023-05-10 22:54 ` [PATCH net-next 2/8] net: phy: realtek: switch interface mode for RTL822x series Chukun Pan
2023-05-10 22:57 ` Daniel Golle
2023-05-10 22:55 ` [PATCH net-next 3/8] net: phy: realtek: use genphy_soft_reset for 2.5G PHYs Daniel Golle
2023-05-10 22:57 ` Daniel Golle
2023-05-10 22:58 ` [PATCH net-next 4/8] net: phy: realtek: disable SGMII in-band AN " Daniel Golle
2023-05-10 22:58 ` [PATCH net-next 5/8] net: phy: realtek: make sure paged read is protected by mutex Daniel Golle
2023-05-10 22:59 ` [PATCH net-next 6/8] net: phy: realtek: use inline functions for 10GbE advertisement Daniel Golle
2023-05-10 22:59 ` [PATCH net-next 7/8] net: phy: realtek: check validity of 10GbE link-partner advertisement Daniel Golle
2023-05-10 23:00 ` [PATCH net-next 8/8] net: phy: realtek: setup ALDPS on RTL8221B Daniel Golle
2023-05-11 0:28 ` [PATCH net-next 0/8] Improvements for RealTek 2.5G Ethernet PHYs Andrew Lunn
2023-05-11 17:14 ` Daniel Golle
2023-05-11 17:30 ` Russell King (Oracle)
2023-05-11 18:09 ` Russell King (Oracle)
2023-05-13 17:52 ` Daniel Golle
2023-05-13 19:24 ` Russell King (Oracle)
2023-05-11 5:29 ` Heiner Kallweit
2023-05-11 11:44 ` Daniel Golle
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